Searched refs:FinalReg (Results 1 – 3 of 3) sorted by relevance
1681 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local1702 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()1703 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()1705 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()1715 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
941 FinalReg = InProlog ? X86::RDX in emitStackProbeInlineWindowsCoreCLR64() local1002 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg) in emitStackProbeInlineWindowsCoreCLR64()1020 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInlineWindowsCoreCLR64()1025 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInlineWindowsCoreCLR64()1027 .addReg(FinalReg) in emitStackProbeInlineWindowsCoreCLR64()
1549 unsigned FinalReg = SubReg; in buildSpillLoadStore() local1619 FinalReg) in buildSpillLoadStore()