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Searched refs:FSQRT (Results 1 – 25 of 54) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fsqrt.mir18 ; SI-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
19 ; SI-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
24 ; VI-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
25 ; VI-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
31 ; GFX9-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
47 ; SI-NEXT: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
48 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FSQRT]](s64)
53 ; VI-NEXT: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
54 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FSQRT]](s64)
60 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FSQRT]](s64)
[all …]
H A Dregbankselect-fsqrt.mir17 ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY1]]
18 ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
35 ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY]]
36 ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfsqrt.mir21 ; FP32: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
22 ; FP32: $f0 = COPY [[FSQRT]](s32)
27 ; FP64: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
28 ; FP64: $f0 = COPY [[FSQRT]](s32)
47 ; FP32: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
48 ; FP32: $d0 = COPY [[FSQRT]](s64)
53 ; FP64: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
54 ; FP64: $d0 = COPY [[FSQRT]](s64)
H A Dfsqrt_vec.mir22 ; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
23 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
46 ; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
47 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
H A Dfsqrt_vec_builtin.mir25 ; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
26 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
49 ; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
50 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfsqrt.mir22 ; FP32: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
23 ; FP32: $f0 = COPY [[FSQRT]](s32)
28 ; FP64: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
29 ; FP64: $f0 = COPY [[FSQRT]](s32)
49 ; FP32: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
50 ; FP32: $d0 = COPY [[FSQRT]](s64)
55 ; FP64: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
56 ; FP64: $d0 = COPY [[FSQRT]](s64)
H A Dfsqrt_vec.mir23 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]]
24 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
48 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]]
49 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3147 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost()
3148 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost()
3155 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss in getTypeBasedIntrinsicInstrCost()
3156 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps in getTypeBasedIntrinsicInstrCost()
3157 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd in getTypeBasedIntrinsicInstrCost()
3158 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd in getTypeBasedIntrinsicInstrCost()
3161 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss in getTypeBasedIntrinsicInstrCost()
3162 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps in getTypeBasedIntrinsicInstrCost()
3163 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd in getTypeBasedIntrinsicInstrCost()
3164 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd in getTypeBasedIntrinsicInstrCost()
[all …]
H A DX86IntrinsicsInfo.h916 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
917 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
1196 X86_INTRINSIC_DATA(avx512fp16_sqrt_ph_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
H A DX86.td516 // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
518 // vector FSQRT has higher throughput than the corresponding NR code.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def96 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h913 FSQRT, enumerator
H A DBasicTTIImpl.h494 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1685 ISD = ISD::FSQRT; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-reciprocal.ll80 ; FSQRT
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp497 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
594 Opcode = ISD::FSQRT; break; in mightUseCTR()
H A DPPCISelLowering.h96 FSQRT, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td553 // FDIV,FSQRT
555 // TODO: Specialize FSQRT for longer latency.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
H A DMipsSEISelLowering.cpp148 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
388 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1912 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
H A DMipsInstrFPU.td543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp194 case ISD::FSQRT: return "fsqrt"; in getOperationName()
H A DLegalizeFloatTypes.cpp125 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1265 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2272 case ISD::FSQRT: in PromoteFloatResult()
2637 case ISD::FSQRT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp367 case ISD::FSQRT: in LegalizeOp()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td121 defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1825 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1850 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1902 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3166 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()

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