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Searched refs:FP_TO_SINT (Results 1 – 25 of 46) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1688 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
1689 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
1690 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
1696 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
1697 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
1698 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
1704 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
1705 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
1720 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
1721 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1778 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
1779 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
1904 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, in getCastInstrCost()
1905 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, in getCastInstrCost()
1906 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, in getCastInstrCost()
1907 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, in getCastInstrCost()
1908 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, in getCastInstrCost()
1909 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, in getCastInstrCost()
1910 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, in getCastInstrCost()
1911 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, in getCastInstrCost()
[all …]
H A DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfp-intrinsics-fptosi-legal.ll3 ; PowerPC SPE is a rare in-tree target that has the FP_TO_SINT node marked
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp704 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
737 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
739 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
741 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
743 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
745 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
747 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
749 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, in getCastInstrCost()
751 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, in getCastInstrCost()
753 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp175 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
458 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
469 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
1059 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
5850 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
9568 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
10358 case ISD::FP_TO_SINT: in LowerOperation()
16724 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx-fp2int.ll4 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfcmp.ll19 ; SET* + FP_TO_SINT
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp54 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
62 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in LoongArchTargetLowering()
132 case ISD::FP_TO_SINT: in LowerOperation()
369 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h819 FP_TO_SINT, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp356 case ISD::FP_TO_SINT: in LegalizeOp()
552 case ISD::FP_TO_SINT: in Promote()
657 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
658 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp842 case ISD::FP_TO_SINT: in SoftenFloatOperand()
965 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
1799 case ISD::FP_TO_SINT: in ExpandFloatOperand()
1931 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2112 case ISD::FP_TO_SINT: in PromoteFloatOperand()
2908 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp356 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeDAG.cpp2601 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2617 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2973 case ISD::FP_TO_SINT: in ExpandNode()
4284 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
4290 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
4517 case ISD::FP_TO_SINT: in PromoteNode()
H A DLegalizeVectorTypes.cpp98 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
644 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
1033 case ISD::FP_TO_SINT: in SplitVectorResult()
2738 case ISD::FP_TO_SINT: in SplitVectorOperand()
3811 case ISD::FP_TO_SINT: in WidenVectorResult()
5456 case ISD::FP_TO_SINT: in WidenVectorOperand()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp293 case ISD::FP_TO_SINT: in getCastInstrCost()
H A DRISCVISelLowering.cpp376 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT, in RISCVTargetLowering()
788 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, in RISCVTargetLowering()
960 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
1834 SDValue Truncated = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, Src); in lowerFTRUNC_FCEIL_FFLOOR()
1909 SDValue Truncated = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, Adjust); in lowerFROUND()
3312 case ISD::FP_TO_SINT: in LowerOperation()
3382 case ISD::FP_TO_SINT: in LowerOperation()
6843 case ISD::FP_TO_SINT: in ReplaceNodeResults()
6848 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in ReplaceNodeResults()
8529 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in performFP_TO_INTCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp219 setOperationAction(ISD::FP_TO_SINT, T, Expand); in initializeHVXLowering()
224 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
292 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
2068 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in LowerHvxConvertFpInt()
2072 if (Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT) { in LowerHvxConvertFpInt()
2405 case ISD::FP_TO_SINT: in LowerHvxOperation()
2471 case ISD::FP_TO_SINT: in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp109 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
199 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
593 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1721 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp360 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
376 setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, in AMDGPUTargetLowering()
1171 case ISD::FP_TO_SINT: in LowerOperation()
1596 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2564 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
2710 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
2715 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp268 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
519 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
529 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
674 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
715 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
8048 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in convertFPToInt()
8095 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INTForReuse()
8152 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
11295 case ISD::FP_TO_SINT: in ReplaceNodeResults()
14078 Opcode = ISD::FP_TO_SINT; in combineElementTruncationToVectorTruncation()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1608 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1610 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3139 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3488 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3494 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll163 ; FP_TO_SINT
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp349 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
360 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1240 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2793 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()

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