Lines Matching refs:FP_TO_SINT
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
458 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
469 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
946 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
947 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
997 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1059 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1061 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
5850 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
5870 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT in LowerFP_TO_INT()
9568 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
9607 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9720 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
10358 case ISD::FP_TO_SINT: in LowerOperation()
16724 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
18618 case ISD::FP_TO_SINT: in PerformDAGCombine()