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Searched refs:FPR (Results 1 – 25 of 63) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
51 // 7: FPR 64-bit value.
55 // 10: FPR 128-bit value.
253 // => FPR 16 to FPR 32|64
254 // => FPR 32 to FPR 64
[all …]
H A DAArch64RegisterBanks.td16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp131 CHECK_VALUEMAP(FPR, 16); in AArch64RegisterBankInfo()
132 CHECK_VALUEMAP(FPR, 32); in AArch64RegisterBankInfo()
133 CHECK_VALUEMAP(FPR, 64); in AArch64RegisterBankInfo()
134 CHECK_VALUEMAP(FPR, 128); in AArch64RegisterBankInfo()
135 CHECK_VALUEMAP(FPR, 256); in AArch64RegisterBankInfo()
136 CHECK_VALUEMAP(FPR, 512); in AArch64RegisterBankInfo()
150 CHECK_VALUEMAP_3OPS(FPR, 32); in AArch64RegisterBankInfo()
151 CHECK_VALUEMAP_3OPS(FPR, 64); in AArch64RegisterBankInfo()
152 CHECK_VALUEMAP_3OPS(FPR, 128); in AArch64RegisterBankInfo()
180 CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32); in AArch64RegisterBankInfo()
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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-regbankselect.mir135 # FPR is used for both floating point and vector registers.
154 # in FPR, but at the use, it should be GPR.
194 # %1 is forced to be into FPR, but its definition actually
312 ; The mapping of G_OR is on FPR.
345 ; The mapping of G_OR is on FPR.
800 # Make sure we map FPEXT on FPR register bank.
835 # Make sure we map FPEXT on FPR register bank.
870 # Make sure we map FPEXT on FPR register bank.
900 # Make sure we map FP16 ABI on FPR register bank.
933 # the value away from FPR (h0).
[all …]
H A Dregbankselect-unmerge-vec.mir14 ; Ensure that the dest regs have FPR since we're unmerging from a vector
38 ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
H A Dregbank-assert-sext.mir65 ; G_ASSERT_SEXT should end up on a FPR.
89 ; G_ASSERT_SEXT should end up on a FPR.
135 ; The G_ASSERT_SEXT should end up on a FPR, and there should be no copy
221 ; This should produce a FPR.
233 ; This should produce a FPR.
343 ; The G_ASSERT_SEXT should end up on a FPR.
H A Dregbank-assert-zext.mir65 ; G_ASSERT_ZEXT should end up on a FPR.
89 ; G_ASSERT_ZEXT should end up on a FPR.
135 ; The G_ASSERT_ZEXT should end up on a FPR, and there should be no copy
221 ; This should produce a FPR.
233 ; This should produce a FPR.
343 ; The G_ASSERT_ZEXT should end up on a FPR.
H A Dregbank-select.mir71 ; if we have two FPR inputs and a GPR output, we should do a floating point
102 ; Same idea as the above test. If the output is an FPR, and one of the
103 ; inputs is an FPR, then it's fewer copies to just do a FCSEL.
H A Dselect-neon-vcvtfxu2fp.mir11 # Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
H A Dregbank-fcmp.mir12 ; Vectors should always end up on a FPR.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h76 void setVarArgsFirstFPR(Register FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
/llvm-project-15.0.7/lldb/source/Plugins/Process/Linux/
H A DNativeRegisterContextLinux_x86_64.cpp220 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize() + sizeof(FPR))
283 return sizeof(FPR); in GetXSTATESize()
287 return sizeof(FPR); in GetXSTATESize()
288 return std::max<std::size_t>(ecx, sizeof(FPR)); in GetXSTATESize()
357 m_xstate.reset(static_cast<FPR *>(std::malloc(xstate_size))); in NativeRegisterContextLinux_x86_64()
528 assert((reg_info->byte_offset - m_fctrl_offset_in_userarea) < sizeof(FPR)); in ReadRegister()
644 sizeof(FPR)); in WriteRegister()
741 ::memcpy(dst, m_xstate.get(), sizeof(FPR)); in ReadAllRegisterValues()
H A DNativeRegisterContextLinux_ppc64le.h91 FPR m_fpr_ppc64le; // floating-point registers including extended register.
H A DNativeRegisterContextLinux_x86_64.h99 std::unique_ptr<FPR, llvm::FreeDeleter>
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGMIR.rst108 registers) and FPR (floating point registers).
111 has to happen in FPR and G_ADD has to happen in GPR. However, even though this
113 happen in both GPR and FPR, and which we want depends on who is going to consume
114 the loaded data. Similarly, G_FNEG can happen in both GPR and FPR. If we assign
115 it to FPR, then we'll use floating point negation. However, if we assign it to
126 AArch64 has three main banks. GPR for integer operations, FPR for floating
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h15 #define FPR_OFFSET(regname) (offsetof(FPR, regname) + sizeof(GPR))
16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
350 } FPR; typedef
H A DRegisterInfos_i386.h28 LLVM_EXTENSION offsetof(FPR, fxsave) + \
34 LLVM_EXTENSION offsetof(FPR, xsave) + \
39 LLVM_EXTENSION offsetof(FPR, xsave) + \
H A DRegisterContextOpenBSD_x86_64.cpp55 FPR fpr;
H A DRegisterInfos_powerpc.h13 #define FPR_OFFSET(regname) (sizeof(GPR) + offsetof(FPR, regname))
14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
H A DRegisterInfos_x86_64.h18 LLVM_EXTENSION offsetof(FPR, fxsave) + \
25 LLVM_EXTENSION offsetof(FPR, xsave) + \
33 LLVM_EXTENSION offsetof(FPR, xsave) + \
38 LLVM_EXTENSION offsetof(FPR, xsave) + \
H A DRegisterContextFreeBSD_x86_64.cpp58 FPR fpr;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td213 // GPR -> FPR
215 // FPR -> GPR
223 // GPR -> FPR
225 // FPR -> GPR
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td50 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
156 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
160 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
166 [!cast<FPR>("F"#!shl(I, 1)),
167 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
171 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dasm-10.ll1 ; Test the FPR constraint "f".
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfastcc_stacksize.ll38 ; No need for Parameter Save Area for calls that utiliizes 8 GPR and 2 FPR.
96 ; Max number of FPR for parameter passing is 13

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