1c51ad483SPavel Labath //===-- NativeRegisterContextLinux_ppc64le.h --------------------*- C++ -*-===//
2aae0a752SEugene Zemtsov //
32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information.
52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6aae0a752SEugene Zemtsov //
7aae0a752SEugene Zemtsov //===----------------------------------------------------------------------===//
8aae0a752SEugene Zemtsov 
9aae0a752SEugene Zemtsov // This implementation is related to the OpenPOWER ABI for Power Architecture
10aae0a752SEugene Zemtsov // 64-bit ELF V2 ABI
11aae0a752SEugene Zemtsov 
12aae0a752SEugene Zemtsov #if defined(__powerpc64__)
13aae0a752SEugene Zemtsov 
14aae0a752SEugene Zemtsov #ifndef lldb_NativeRegisterContextLinux_ppc64le_h
15aae0a752SEugene Zemtsov #define lldb_NativeRegisterContextLinux_ppc64le_h
16aae0a752SEugene Zemtsov 
17aae0a752SEugene Zemtsov #include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
18aae0a752SEugene Zemtsov #include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
19aae0a752SEugene Zemtsov 
20aae0a752SEugene Zemtsov #define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
212ad48212SJames Y Knight #include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
22aae0a752SEugene Zemtsov #undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
23aae0a752SEugene Zemtsov 
24aae0a752SEugene Zemtsov namespace lldb_private {
25aae0a752SEugene Zemtsov namespace process_linux {
26aae0a752SEugene Zemtsov 
27aae0a752SEugene Zemtsov class NativeProcessLinux;
28aae0a752SEugene Zemtsov 
29aae0a752SEugene Zemtsov class NativeRegisterContextLinux_ppc64le : public NativeRegisterContextLinux {
30aae0a752SEugene Zemtsov public:
31aae0a752SEugene Zemtsov   NativeRegisterContextLinux_ppc64le(const ArchSpec &target_arch,
32d37349f3SPavel Labath                                      NativeThreadProtocol &native_thread);
33aae0a752SEugene Zemtsov 
34aae0a752SEugene Zemtsov   uint32_t GetRegisterSetCount() const override;
35aae0a752SEugene Zemtsov 
36aae0a752SEugene Zemtsov   uint32_t GetUserRegisterCount() const override;
37aae0a752SEugene Zemtsov 
38aae0a752SEugene Zemtsov   const RegisterSet *GetRegisterSet(uint32_t set_index) const override;
39aae0a752SEugene Zemtsov 
40aae0a752SEugene Zemtsov   Status ReadRegister(const RegisterInfo *reg_info,
41aae0a752SEugene Zemtsov                       RegisterValue &reg_value) override;
42aae0a752SEugene Zemtsov 
43aae0a752SEugene Zemtsov   Status WriteRegister(const RegisterInfo *reg_info,
44aae0a752SEugene Zemtsov                        const RegisterValue &reg_value) override;
45aae0a752SEugene Zemtsov 
46*c2f64601SJonas Devlieghere   Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
47aae0a752SEugene Zemtsov 
48aae0a752SEugene Zemtsov   Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
49aae0a752SEugene Zemtsov 
504ebdee0aSBruce Mitchener   // Hardware watchpoint management functions
51c51ad483SPavel Labath 
52c51ad483SPavel Labath   uint32_t NumSupportedHardwareWatchpoints() override;
53c51ad483SPavel Labath 
54c51ad483SPavel Labath   uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size,
55c51ad483SPavel Labath                                  uint32_t watch_flags) override;
56c51ad483SPavel Labath 
57c51ad483SPavel Labath   bool ClearHardwareWatchpoint(uint32_t hw_index) override;
58c51ad483SPavel Labath 
59c51ad483SPavel Labath   Status GetWatchpointHitIndex(uint32_t &wp_index,
60c51ad483SPavel Labath                                lldb::addr_t trap_addr) override;
61c51ad483SPavel Labath 
62c51ad483SPavel Labath   lldb::addr_t GetWatchpointHitAddress(uint32_t wp_index) override;
63c51ad483SPavel Labath 
64c51ad483SPavel Labath   lldb::addr_t GetWatchpointAddress(uint32_t wp_index) override;
65c51ad483SPavel Labath 
66c51ad483SPavel Labath   uint32_t GetWatchpointSize(uint32_t wp_index);
67c51ad483SPavel Labath 
68c51ad483SPavel Labath   bool WatchpointIsEnabled(uint32_t wp_index);
69c51ad483SPavel Labath 
70aae0a752SEugene Zemtsov protected:
71e6a66105SPavel Labath   bool IsVMX(unsigned reg);
72e6a66105SPavel Labath 
73e6a66105SPavel Labath   bool IsVSX(unsigned reg);
74e6a66105SPavel Labath 
75e6a66105SPavel Labath   Status ReadVMX();
76e6a66105SPavel Labath 
77e6a66105SPavel Labath   Status WriteVMX();
78e6a66105SPavel Labath 
79e6a66105SPavel Labath   Status ReadVSX();
80e6a66105SPavel Labath 
81e6a66105SPavel Labath   Status WriteVSX();
82e6a66105SPavel Labath 
GetGPRBuffer()83aae0a752SEugene Zemtsov   void *GetGPRBuffer() override { return &m_gpr_ppc64le; }
84aae0a752SEugene Zemtsov 
GetFPRBuffer()85e6a66105SPavel Labath   void *GetFPRBuffer() override { return &m_fpr_ppc64le; }
86e6a66105SPavel Labath 
GetFPRSize()87e6a66105SPavel Labath   size_t GetFPRSize() override { return sizeof(m_fpr_ppc64le); }
88e6a66105SPavel Labath 
89aae0a752SEugene Zemtsov private:
90aae0a752SEugene Zemtsov   GPR m_gpr_ppc64le; // 64-bit general purpose registers.
91e6a66105SPavel Labath   FPR m_fpr_ppc64le; // floating-point registers including extended register.
92e6a66105SPavel Labath   VMX m_vmx_ppc64le; // VMX registers.
93e6a66105SPavel Labath   VSX m_vsx_ppc64le; // Last lower bytes from first VSX registers.
94aae0a752SEugene Zemtsov 
95aae0a752SEugene Zemtsov   bool IsGPR(unsigned reg) const;
96c51ad483SPavel Labath 
97e6a66105SPavel Labath   bool IsFPR(unsigned reg) const;
98e6a66105SPavel Labath 
99e6a66105SPavel Labath   bool IsVMX(unsigned reg) const;
100e6a66105SPavel Labath 
101e6a66105SPavel Labath   bool IsVSX(unsigned reg) const;
102e6a66105SPavel Labath 
103e6a66105SPavel Labath   uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
104e6a66105SPavel Labath 
105e6a66105SPavel Labath   uint32_t CalculateVmxOffset(const RegisterInfo *reg_info) const;
106e6a66105SPavel Labath 
107e6a66105SPavel Labath   uint32_t CalculateVsxOffset(const RegisterInfo *reg_info) const;
108e6a66105SPavel Labath 
109c51ad483SPavel Labath   Status ReadHardwareDebugInfo();
110c51ad483SPavel Labath 
111c51ad483SPavel Labath   Status WriteHardwareDebugRegs();
112c51ad483SPavel Labath 
113c51ad483SPavel Labath   // Debug register info for hardware watchpoints management.
114c51ad483SPavel Labath   struct DREG {
115c51ad483SPavel Labath     lldb::addr_t address;   // Breakpoint/watchpoint address value.
116c51ad483SPavel Labath     lldb::addr_t hit_addr;  // Address at which last watchpoint trigger
117c51ad483SPavel Labath                             // exception occurred.
118c51ad483SPavel Labath     lldb::addr_t real_addr; // Address value that should cause target to stop.
119c51ad483SPavel Labath     uint32_t control;       // Breakpoint/watchpoint control value.
120c51ad483SPavel Labath     uint32_t refcount;      // Serves as enable/disable and reference counter.
121c51ad483SPavel Labath     long slot;              // Saves the value returned from PTRACE_SETHWDEBUG.
122c51ad483SPavel Labath     int mode;               // Defines if watchpoint is read/write/access.
123c51ad483SPavel Labath   };
124c51ad483SPavel Labath 
125c51ad483SPavel Labath   std::array<DREG, 4> m_hwp_regs;
126c51ad483SPavel Labath 
127c51ad483SPavel Labath   // 16 is just a maximum value, query hardware for actual watchpoint count
128c51ad483SPavel Labath   uint32_t m_max_hwp_supported = 16;
129c51ad483SPavel Labath   uint32_t m_max_hbp_supported = 16;
130c51ad483SPavel Labath   bool m_refresh_hwdebug_info = true;
131aae0a752SEugene Zemtsov };
132aae0a752SEugene Zemtsov 
133aae0a752SEugene Zemtsov } // namespace process_linux
134aae0a752SEugene Zemtsov } // namespace lldb_private
135aae0a752SEugene Zemtsov 
136aae0a752SEugene Zemtsov #endif // #ifndef lldb_NativeRegisterContextLinux_ppc64le_h
137aae0a752SEugene Zemtsov 
138aae0a752SEugene Zemtsov #endif // defined(__powerpc64__)
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