[lldb] Update the NativeRegisterContext to take a WritableMemoryBuffer

[lldb] Rename NativeRegisterContext{Watchpoint => DBReg}_x86

Differential Revision: https://reviews.llvm.org/D97210

[lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86

Differential Revision: https://reviews.llvm.org/D90119

[lldb-server][linux] Add ability to allocate memory

This patch adds support for the _M and _m gdb-remote packets, which
(de)allocate memory in the inferior. This works by "injecting" a
m(un)map sysc

[lldb-server][linux] Add ability to allocate memory

This patch adds support for the _M and _m gdb-remote packets, which
(de)allocate memory in the inferior. This works by "injecting" a
m(un)map syscall into the inferior. This consists of:
- finding an executable page of memory
- writing the syscall opcode to it
- setting up registers according to the os syscall convention
- single stepping over the syscall

The advantage of this approach over calling the mmap function is that
this works even in case the mmap function is buggy or unavailable. The
disadvantage is it is more platform-dependent, which is why this patch
only works on X86 (_32 and _64) right now. Adding support for other
linux architectures should be easy and consist of defining the
appropriate syscall constants. Adding support for other OSes depends on
the its ability to do a similar trick.

Differential Revision: https://reviews.llvm.org/D89124

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[lldb] Fix offset intersection bug between MPX and AVX registers

Summary:
This change increases the offset of MPX registers (by 128) so they
do not overlap with the offset associated with AVX regist

[lldb] Fix offset intersection bug between MPX and AVX registers

Summary:
This change increases the offset of MPX registers (by 128) so they
do not overlap with the offset associated with AVX registers. That was
causing MPX data in GDBRemoteRegisterContext::m_reg_data to get overwritten.

Reviewers: labath

Reviewed By: labath

Subscribers: JDevlieghere, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D68874

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[Linux/x86] Fix writing of non-gpr registers on newer processors

Summary:
We're using ptrace(PTRACE_SETREGSET, NT_X86_XSTATE) to write all non-gpt
registers on x86 linux. Unfortunately, this method

[Linux/x86] Fix writing of non-gpr registers on newer processors

Summary:
We're using ptrace(PTRACE_SETREGSET, NT_X86_XSTATE) to write all non-gpt
registers on x86 linux. Unfortunately, this method has a quirk, where
the kernel rejects all attempts to write to this area if one supplies a
buffer which is smaller than the area size (even though the kernel will
happily accept partial reads from it).

This means that if the CPU supports some new registers/extensions that
we don't know about (in my case it was the PKRU extension), we will fail
to write *any* non-gpr registers, even those that we know about.

Since this is a situation that's likely to appear again and again, I add
code to NativeRegisterContextLinux_x86_64 to detect the runtime size of
the area, and allocate an appropriate buffer. This does not mean that we
will start automatically supporting all new extensions, but it does mean
that the new extensions will not prevent the old ones from working.

This fixes tests attempting to write to non-gpr registers on new intel
processors (cca Kaby Lake Refresh).

Reviewers: jankratochvil, davezarzycki

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D59991

llvm-svn: 357376

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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Kill struct IOVEC

struct iovec is used as an interface to system (posix) api's. As such,
we shouldn't be using it in os-independent code, and we shouldn't be
defining our own iovec replacements.

Fo

Kill struct IOVEC

struct iovec is used as an interface to system (posix) api's. As such,
we shouldn't be using it in os-independent code, and we shouldn't be
defining our own iovec replacements.

Fortunately, its usage was not very widespread, so the removal was very
easy -- I simply moved a couple declarations into os-specific code.

llvm-svn: 319536

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Fix floating point register write on new x86 linux kernels

Summary:
New linux kernels (on systems that support the XSAVES instruction) will
not update the inferior registers unless the corresponding

Fix floating point register write on new x86 linux kernels

Summary:
New linux kernels (on systems that support the XSAVES instruction) will
not update the inferior registers unless the corresponding flag in the
XSAVE header is set. Normally this flag will be set in our image of the
XSAVE area (since we obtained it from the kernel), but if the inferior
has never used the corresponding register set, the respective flag can
be clear.

This fixes the issue by making sure we explicitly set the flags
corresponding to the registers we modify. I don't try to precisely match
the flags to set on each write, as the rules could get quite complicated
-- I use a simpler over-approximation instead.

This was already caught by test_fp_register_write, but that was only
because the code that ran before main() did not use some of the register
sets. Since nothing in this test relies on being stopped in main(), I
modify the test to stop at the entry point instead, so we can be sure
the inferior did not have a chance to access these registers.

Reviewers: clayborg, valentinagiusti

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D40434

llvm-svn: 319161

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Clean up NativeRegisterContext

Summary:
This commit removes the concrete_frame_idx member from
NativeRegisterContext and related functions, which was always set to
zero and never used.

I also chang

Clean up NativeRegisterContext

Summary:
This commit removes the concrete_frame_idx member from
NativeRegisterContext and related functions, which was always set to
zero and never used.

I also change the native thread class to store a NativeRegisterContext
as a unique_ptr (documenting the ownership) and make sure it is always
initialized (most of the code was already blindly dereferencing the
register context pointer, assuming it would always be present -- this
makes its treatment consistent).

Reviewers: eugene, clayborg, krytarowski

Subscribers: aemerson, sdardis, nemanjai, javed.absar, arichardson, kristof.beyls, kbarton, uweigand, alexandreyy, lldb-commits

Differential Revision: https://reviews.llvm.org/D39837

llvm-svn: 317881

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Rename Error -> Status.

This renames the LLDB error class to Status, as discussed
on the lldb-dev mailing list.

A change of this magnitude cannot easily be done without
find and replace, but that h

Rename Error -> Status.

This renames the LLDB error class to Status, as discussed
on the lldb-dev mailing list.

A change of this magnitude cannot easily be done without
find and replace, but that has potential to catch unwanted
occurrences of common strings such as "Error". Every effort
was made to find all the obvious things such as the word "Error"
appearing in a string, etc, but it's possible there are still
some lingering occurences left around. Hopefully nothing too
serious.

llvm-svn: 302872

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Refactor NativeRegisterContextLinux_x86_64 code.

This patch refactors the way the XState type is checked and, in order to
simplify the code, it removes the usage of the 'cpuid' instruction: just che

Refactor NativeRegisterContextLinux_x86_64 code.

This patch refactors the way the XState type is checked and, in order to
simplify the code, it removes the usage of the 'cpuid' instruction: just checking
if the ptrace calls done throuhg ReadFPR is enough to verify both if there is
HW support and if there is kernel support. Also the XCR0 bits are enough to check if
there is both HW and kernel support for AVX and MPX.

Differential Revision: https://reviews.llvm.org/D24764

llvm-svn: 282072

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Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.

Reviewers: labath, clayborg, zturner

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24578

llv

Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.

Reviewers: labath, clayborg, zturner

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24578

llvm-svn: 281528

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Use Intel CPU flags to determine target supported features.

Summary:
This patch uses the instruction CPUID to verify that FXSAVE, XSAVE, AVX
and MPX are supported by the target hardware. In case the

Use Intel CPU flags to determine target supported features.

Summary:
This patch uses the instruction CPUID to verify that FXSAVE, XSAVE, AVX
and MPX are supported by the target hardware. In case the HW supports XSAVE,
and at least one of the extended register sets, it further checks if the
target software has the kernel support for such features, by verifying that
their XSAVE part is correctly managed.

Differential Revision: https://reviews.llvm.org/D24559

llvm-svn: 281507

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Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

Summary: Signed-off-by: Valentina Giusti <[email protected]>

Reviewers: dvlahovski, granata.enrico, clayborg

Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

Summary: Signed-off-by: Valentina Giusti <[email protected]>

Reviewers: dvlahovski, granata.enrico, clayborg, labath

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24255

llvm-svn: 280942

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*** This commit represents a complete reformatting of the LLDB source code
*** to conform to clang-format’s LLVM style. This kind of mass change has
*** two obvious implications:

Firstly, merging t

*** This commit represents a complete reformatting of the LLDB source code
*** to conform to clang-format’s LLVM style. This kind of mass change has
*** two obvious implications:

Firstly, merging this particular commit into a downstream fork may be a huge
effort. Alternatively, it may be worth merging all changes up to this commit,
performing the same reformatting operation locally, and then discarding the
merge for this particular commit. The commands used to accomplish this
reformatting were as follows (with current working directory as the root of
the repository):

find . \( -iname "*.c" -or -iname "*.cpp" -or -iname "*.h" -or -iname "*.mm" \) -exec clang-format -i {} +
find . -iname "*.py" -exec autopep8 --in-place --aggressive --aggressive {} + ;

The version of clang-format used was 3.9.0, and autopep8 was 1.2.4.

Secondly, “blame” style tools will generally point to this commit instead of
a meaningful prior commit. There are alternatives available that will attempt
to look through this change and find the appropriate prior commit. YMMV.

llvm-svn: 280751

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Revert "Intel(R) Memory Protection Extensions (Intel(R) MPX) support."

This reverts commit rL280668 because the register tests fail on i386
Linux.

I investigated a little bit what causes the failur

Revert "Intel(R) Memory Protection Extensions (Intel(R) MPX) support."

This reverts commit rL280668 because the register tests fail on i386
Linux.

I investigated a little bit what causes the failure - there are missing
registers when running 'register read -a'.
This is the output I got at the bottom:
"""
...
Memory Protection Extensions:
bnd0 = {0x0000000000000000 0x0000000000000000}
bnd1 = {0x0000000000000000 0x0000000000000000}
bnd2 = {0x0000000000000000 0x0000000000000000}
bnd3 = {0x0000000000000000 0x0000000000000000}

unknown:
2 registers were unavailable.
"""

Also looking at the packets exchanged between the client and server:
"""
...
history[308] tid=0x7338 < 19> send packet: $qRegisterInfo4a#d7
history[309] tid=0x7338 < 130> read packet:
$name:bnd0;bitsize:128;offset:1032;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:101;dwarf:101;#48
history[310] tid=0x7338 < 19> send packet: $qRegisterInfo4b#d8
history[311] tid=0x7338 < 130> read packet:
$name:bnd1;bitsize:128;offset:1048;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:102;dwarf:102;#52
history[312] tid=0x7338 < 19> send packet: $qRegisterInfo4c#d9
history[313] tid=0x7338 < 130> read packet:
$name:bnd2;bitsize:128;offset:1064;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:103;dwarf:103;#53
history[314] tid=0x7338 < 19> send packet: $qRegisterInfo4d#da
history[315] tid=0x7338 < 130> read packet:
$name:bnd3;bitsize:128;offset:1080;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:104;dwarf:104;#54
history[316] tid=0x7338 < 19> send packet: $qRegisterInfo4e#db
history[317] tid=0x7338 < 76> read packet:
$name:bndcfgu;bitsize:64;offset:1096;encoding:vector;format:vector-uint8;#99
history[318] tid=0x7338 < 19> send packet: $qRegisterInfo4f#dc
history[319] tid=0x7338 < 78> read packet:
$name:bndstatus;bitsize:64;offset:1104;encoding:vector;format:vector-uint8;#8e
...
"""

The bndcfgu and bndstatus registers don't have the 'Memory Protections
Extension' set. I looked at the code and it seems that that is set
correctly.

So I'm not sure what's the problem or where does it come from.

Also there is a second failure related to something like this in the
tests:
"""
registerSet.GetName().lower()
"""

For some reason the registerSet.GetName() returns None.

llvm-svn: 280703

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Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

Summary:

The Intel(R) Memory Protection Extensions (Intel(R) MPX) associates pointers
to bounds, against which the software can check m

Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

Summary:

The Intel(R) Memory Protection Extensions (Intel(R) MPX) associates pointers
to bounds, against which the software can check memory references to
prevent out of bound memory access.

This patch allows accessing the MPX registers:
* bnd0-3: 128-bit registers to hold the bound values,
* bndcfgu, bndstatus: 64-bit configuration registers,

This patch also adds read/write tests for the MPX registers in the register
command tests and adds a new subdirectory for MPX specific tests.

Signed-off-by: Valentina Giusti <[email protected]>

Reviewers: labath, granata.enrico, lldb-commits, clayborg

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24187

llvm-svn: 280668

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Bug 24457 - X87 FPU Special Purpose Registers

Summary:
- For 'register read --all' command on x86_64-Linux Platform:

-- Provide correct values of X87 FPU Special Purpose Registers
--

Bug 24457 - X87 FPU Special Purpose Registers

Summary:
- For 'register read --all' command on x86_64-Linux Platform:

-- Provide correct values of X87 FPU Special Purpose Registers
-- Both 32-bit & 64-bit inferiors give correct values on this
Platform

- Added a Test Vector:
-- To verify the expected behaviour of the command

Signed-off-by: Abhishek Aggarwal <[email protected]>

Reviewers: ashok.thirumurthi, granata.enrico, tfiala, clayborg

Differential Revision: http://reviews.llvm.org/D12592

llvm-svn: 246955

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Move register reading form NativeProcessLinux to NativeRegisterContextLinux*

This change reorganize the register read/write code inside lldb-server on Linux
with moving the architecture independent

Move register reading form NativeProcessLinux to NativeRegisterContextLinux*

This change reorganize the register read/write code inside lldb-server on Linux
with moving the architecture independent code into a new class called
NativeRegisterContextLinux and all of the architecture dependent code into the
appropriate NativeRegisterContextLinux_* class. As part of it the compilation of
the architecture specific register contexts are only compiled on the specific
architecture because they can't be used in other cases.

The purpose of this change is to remove a lot of duplicated code from the different
register contexts and to remove the architecture dependent codes from the global
NativeProcessLinux class.

Differential revision: http://reviews.llvm.org/D9935

llvm-svn: 238196

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This patch adds support for setting/clearing hardware watchpoints and breakpoints on AArch64 (Arm v8) 64-bit hardware.

http://reviews.llvm.org/D9706

llvm-svn: 237419

Move several plugin to its own namespace

Affected paths:
* Plugins/Platform/Android/*
* Plugins/Platform/Linux/*
* Plugins/Platform/gdb-server/*
* Plugins/Process/Linux/*
* Plugins/Process/gdb-remot

Move several plugin to its own namespace

Affected paths:
* Plugins/Platform/Android/*
* Plugins/Platform/Linux/*
* Plugins/Platform/gdb-server/*
* Plugins/Process/Linux/*
* Plugins/Process/gdb-remote/*

Differential revision: http://reviews.llvm.org/D8654

llvm-svn: 233679

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Report watchpoint hits during single stepping.

Summary:
Reorganized NativeProcessLinux::MonitorSIGTRAP to check for watchpoint hits on
TRAP_TRACE.

Added test for stepping over watchpoints.

https:/

Report watchpoint hits during single stepping.

Summary:
Reorganized NativeProcessLinux::MonitorSIGTRAP to check for watchpoint hits on
TRAP_TRACE.

Added test for stepping over watchpoints.

https://llvm.org/bugs/show_bug.cgi?id=22814

Reviewers: ovyalov, tberghammer, vharron, clayborg

Subscribers: jingham, labath, lldb-commits

Differential Revision: http://reviews.llvm.org/D8404

llvm-svn: 232784

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Report stopped by trace if none of the watchpoint was hit

Some linux kernel reports a watchpoint hit after single stepping even
when no watchpoint was hit. This CL looks for a watchpoint which was h

Report stopped by trace if none of the watchpoint was hit

Some linux kernel reports a watchpoint hit after single stepping even
when no watchpoint was hit. This CL looks for a watchpoint which was hit
and reports a stop by trace if it haven't found any.

Differential revision: http://reviews.llvm.org/D8081

llvm-svn: 232482

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Report the actual user register count from NativeRegisterContextLinux_x86_64

Thic change have effect wehn the AVX registers aren't available with
reporting the count of user registers without them.

Report the actual user register count from NativeRegisterContextLinux_x86_64

Thic change have effect wehn the AVX registers aren't available with
reporting the count of user registers without them.

Differential revision: http://reviews.llvm.org/D8111

llvm-svn: 231638

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