| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 91 DAG_FUNCTION(powi, 2, 1, experimental_constrained_powi, FPOWI)
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 917 FPOWI, enumerator
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 281 case ISD::FPOWI: return "fpowi"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 113 case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break; in SoftenFloatResult()
1254 case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break; in ExpandFloatResult()
2291 case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break; in PromoteFloatResult()
2656 case ISD::FPOWI: R = SoftPromoteHalfRes_FPOWI(N); break; in SoftPromoteHalfResult()
|
| H A D | LegalizeVectorTypes.cpp | 58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
351 return DAG.getNode(ISD::FPOWI, SDLoc(N), in ScalarizeVecRes_FPOWI()
960 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; in SplitVectorResult()
1440 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); in SplitVecRes_FPOWI()
1441 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); in SplitVecRes_FPOWI()
3796 case ISD::FPOWI: in WidenVectorResult()
|
| H A D | LegalizeVectorOps.cpp | 370 case ISD::FPOWI: in LegalizeOp()
|
| H A D | LegalizeDAG.cpp | 4109 case ISD::FPOWI: in ConvertNodeToLibcall()
4809 case ISD::FPOWI: { in PromoteNode()
|
| H A D | LegalizeIntegerTypes.cpp | 1702 case ISD::FPOWI: in PromoteIntegerOperand()
|
| H A D | SelectionDAG.cpp | 4665 case ISD::FPOWI: in isKnownNeverNaN()
|
| H A D | SelectionDAGBuilder.cpp | 5398 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); in ExpandPowI()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 842 setOperationAction({ISD::FROUND, ISD::FROUNDEVEN, ISD::FPOWI}, VT, Expand); in initActions()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 156 case ISD::FPOWI: in fp16SrcZerosHighBits()
|
| H A D | SIISelLowering.cpp | 393 setOperationAction({ISD::FPOW, ISD::FPOWI}, MVT::f16, Promote); in SITargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 333 ISD::FPOW, ISD::FPOWI, ISD::FCOS, ISD::FSIN, in RISCVTargetLowering()
343 setOperationAction(ISD::FPOWI, MVT::i32, Custom); in RISCVTargetLowering()
3293 case ISD::FPOWI: { in LowerOperation()
3301 DAG.getNode(ISD::FPOWI, DL, MVT::f32, Op0, Op.getOperand(1)); in LowerOperation()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 144 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in MipsSETargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 590 for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI, in AArch64TargetLowering()
1326 setOperationAction(ISD::FPOWI, VT, Expand); in AArch64TargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1169 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1522 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in ARMTargetLowering()
|