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Searched refs:FMul (Results 1 – 25 of 87) sorted by relevance

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/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Darithmetic-ops.mlir40 // spv.FMul
44 // CHECK: spv.FMul
45 %0 = spv.FMul %arg, %arg : f32
50 // CHECK: spv.FMul
51 %0 = spv.FMul %arg, %arg : vector<4xf32>
59 %0 = spv.FMul %arg, %arg : i32
67 %0 = spv.FMul %arg, %arg : bf16
75 %0 = spv.FMul %arg, %arg : tensor<4xf32>
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp115 case Instruction::FMul: return Instruction::Mul; in mapBinOpcode()
215 case Instruction::FMul: in walkBackwards()
301 case Instruction::FMul: { in calcRange()
489 case Instruction::FMul: in convert()
H A DReassociate.cpp349 assert((Opcode == Instruction::Mul || Opcode == Instruction::FMul) && in IncorporateWeight()
596 (Opcode == Instruction::FMul && match(Op, m_FNeg(m_Value())))) && in LinearizeExprTree()
1158 BinaryOperator *BO = isReassociableOp(V, Instruction::Mul, Instruction::FMul); in RemoveFactorFromExpression()
1233 BinaryOperator *BO = isReassociableOp(V, Instruction::Mul, Instruction::FMul); in FindSingleUseMultiplyFactors()
1648 isReassociableOp(Ops[i].Op, Instruction::Mul, Instruction::FMul); in OptimizeAdd()
1720 isReassociableOp(Ops[i].Op, Instruction::Mul, Instruction::FMul); in OptimizeAdd()
2008 case Instruction::FMul: in OptimizeExpression()
2085 case Instruction::FMul: in getNegatibleInsts()
2293 if (isReassociableOp(Op, Instruction::FMul) && in OptimizeInst()
2295 !isReassociableOp(I->user_back(), Instruction::FMul))) { in OptimizeInst()
[all …]
H A DSpeculativeExecution.cpp242 case Instruction::FMul: in ComputeSpeculationCost()
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Linking/ModuleCombiner/
H A Ddeduplication.mlir153 // CHECK-NEXT: %[[MUL:.+]] = spv.FMul %[[ADD]], %[[ARG2]] : f32
158 // CHECK-NEXT: %[[MUL:.+]] = spv.FMul %[[ADD]], %[[ARG1]] : f32
166 %mul = spv.FMul %add, %c: f32
174 %mul = spv.FMul %add, %b: f32
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Darithmetic-ops-to-llvm.mlir112 // spv.FMul
118 %0 = spv.FMul %arg0, %arg1 : f32
125 %0 = spv.FMul %arg0, %arg1 : vector<2xf32>
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DIVDescriptors.cpp409 if (IsASelect && (Kind == RecurKind::FAdd || Kind == RecurKind::FMul) && in AddReductionVar()
755 return InstDesc(Kind == RecurKind::FMul, SI); in isConditionalRdxPattern()
782 case Instruction::FMul: in isRecurrenceInstr()
783 return InstDesc(Kind == RecurKind::FMul, I, in isRecurrenceInstr()
790 if (Kind == RecurKind::FAdd || Kind == RecurKind::FMul) in isRecurrenceInstr()
889 if (AddReductionVar(Phi, RecurKind::FMul, TheLoop, FMF, RedDes, DB, AC, DT, in isReductionPHI()
1065 case RecurKind::FMul: in getRecurrenceIdentity()
1114 case RecurKind::FMul: in getOpcode()
1115 return Instruction::FMul; in getOpcode()
/llvm-project-15.0.7/mlir/test/Target/SPIRV/
H A Darithmetic-ops.mlir5 // CHECK: {{%.*}}= spv.FMul {{%.*}}, {{%.*}} : f32
6 %0 = spv.FMul %arg0, %arg1 : f32
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXTargetTransformInfo.cpp317 return {Instruction::FMul, FTZ_Any}; in simplifyNvvmIntrinsic()
319 return {Instruction::FMul, FTZ_MustBeOff}; in simplifyNvvmIntrinsic()
321 return {Instruction::FMul, FTZ_MustBeOn}; in simplifyNvvmIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOs16.cpp84 case Instruction::FMul: in needsFP()
/llvm-project-15.0.7/mlir/test/Conversion/VectorToSPIRV/
H A Dvector-to-spirv.mlir258 // CHECK: %[[ADD0:.+]] = spv.FMul %[[S0]], %[[S1]]
259 // CHECK: %[[ADD1:.+]] = spv.FMul %[[ADD0]], %[[S2]]
260 // CHECK: %[[ADD2:.+]] = spv.FMul %[[ADD1]], %[[S]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfmul-inseltpoison.ll7 ; Don't crash when attempting to cast a constant FMul to an instruction.
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExpandReductions.cpp34 return Instruction::FMul; in getOpcode()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVArithmeticOps.td143 def SPV_FMulOp : SPV_ArithmeticBinaryOp<"FMul", SPV_Float, [Commutative]> {
159 fmul-op ::= `spv.FMul` ssa-use, ssa-use
166 %4 = spv.FMul %0, %1 : f32
167 %5 = spv.FMul %2, %3 : vector<4xf32>
/llvm-project-15.0.7/llvm/lib/FuzzMutate/
H A DOperations.cpp48 Ops.push_back(binOpDescriptor(1, Instruction::FMul)); in describeFuzzerFloatOps()
113 case Instruction::FMul: in binOpDescriptor()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def54 DAG_INSTRUCTION(FMul, 2, 1, experimental_constrained_fmul, FMUL)
H A DInstruction.def152 HANDLE_BINARY_INST(18, FMul , BinaryOperator)
H A DOperator.h307 case Instruction::FMul: in classof()
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/
H A DExecutionEngine.cpp777 case Instruction::FMul: in getConstantValue()
812 case Instruction::FMul: in getConstantValue()
827 case Instruction::FMul: in getConstantValue()
851 case Instruction::FMul: in getConstantValue()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DIVDescriptors.h47 FMul, ///< Product of floats. enumerator
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVELaneInterleavingPass.cpp236 case Instruction::FMul: in tryInterleave()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp431 assert((Opcode == Instruction::FMul || Opcode == Instruction::FDiv) && in foldFPSignBitOps()
509 ConstantFoldBinaryOpOperands(Instruction::FMul, C, C1, DL); in visitFMul()
534 Instruction::FMul, C, C1, DL)) { in visitFMul()
542 Instruction::FMul, C, C1, DL)) { in visitFMul()
1274 NewC = ConstantFoldBinaryOpOperands(Instruction::FMul, C, C2, DL); in foldFDivConstantDividend()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSimplifyLibCalls.cpp1801 Value *FMul = B.CreateFMul(BaseFn->getArgOperand(0), Expo, "mul"); in replacePowWithExp() local
1804 FMul, ExpName) in replacePowWithExp()
1805 : emitUnaryFloatFnCall(FMul, TLI, LibFnDouble, LibFnFloat, in replacePowWithExp()
1848 Value *FMul = B.CreateFMul(Expo, ConstantFP::get(Ty, N), "mul"); in replacePowWithExp() local
1852 FMul, "exp2")); in replacePowWithExp()
1854 return copyFlags(*Pow, emitUnaryFloatFnCall(FMul, TLI, LibFunc_exp2, in replacePowWithExp()
1883 Value *FMul = B.CreateFMul(Log, Expo, "mul"); in replacePowWithExp() local
1887 FMul, "exp2")); in replacePowWithExp()
1890 return copyFlags(*Pow, emitUnaryFloatFnCall(FMul, TLI, LibFunc_exp2, in replacePowWithExp()
2318 if (!I || I->getOpcode() != Instruction::FMul || !I->isFast()) in optimizeSqrt()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp1029 auto *FMul = IC.Builder.CreateFMulFMF(Op0, Op1, &II); in instCombineIntrinsic() local
1030 FMul->takeName(&II); in instCombineIntrinsic()
1031 return IC.replaceInstUsesWith(II, FMul); in instCombineIntrinsic()
/llvm-project-15.0.7/llvm/lib/IR/
H A DInstruction.cpp372 case FMul: return "fmul"; in getOpcodeName()
761 case FMul: in isAssociative()

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