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Searched refs:FMAXNUM (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-amdgcn.rsq.clamp.mir62 ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
63 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
H A Dregbankcombiner-clamp-minmax-const.mir446 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMUL]], [[COPY2]]
449 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY3]]
572 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY3]]
573 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
H A Dregbankcombiner-fmed3-minmax-const.mir472 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
475 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY2]]
508 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY2]]
509 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
H A Dlegalize-fmaxnum.mir64 ; SI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
65 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
71 ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
72 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
78 ; GFX9-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
79 ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
H A Dcombine-foldable-fneg.mir18 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FNEG]], [[FNEG1]]
19 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-fp-min-max-intrinsics.ll36 ; CHECK: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
37 ; CHECK: $s0 = COPY [[FMAXNUM]](s32)
H A Dlegalize-fmaxnum.mir22 ; NO-FP16: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
23 ; NO-FP16: %maxnum:_(s16) = G_FPTRUNC [[FMAXNUM]](s32)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def85 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3001 { ISD::FMAXNUM, MVT::f32, 2 }, in getTypeBasedIntrinsicInstrCost()
3002 { ISD::FMAXNUM, MVT::v4f32, 2 }, in getTypeBasedIntrinsicInstrCost()
3003 { ISD::FMAXNUM, MVT::v8f32, 2 }, in getTypeBasedIntrinsicInstrCost()
3004 { ISD::FMAXNUM, MVT::v16f32, 2 }, in getTypeBasedIntrinsicInstrCost()
3005 { ISD::FMAXNUM, MVT::f64, 2 }, in getTypeBasedIntrinsicInstrCost()
3006 { ISD::FMAXNUM, MVT::v2f64, 2 }, in getTypeBasedIntrinsicInstrCost()
3007 { ISD::FMAXNUM, MVT::v4f64, 2 }, in getTypeBasedIntrinsicInstrCost()
3008 { ISD::FMAXNUM, MVT::v8f64, 2 }, in getTypeBasedIntrinsicInstrCost()
3245 { ISD::FMAXNUM, MVT::f64, 4 }, in getTypeBasedIntrinsicInstrCost()
3246 { ISD::FMAXNUM, MVT::v2f64, 4 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h944 FMAXNUM, enumerator
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGenericOpcode.rst511 The return value of (FMAXNUM 0.0, -0.0) could be either 0.0 or -0.0.
524 definition. This differs from FMAXNUM in the handling of signaling NaNs. If one
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp509 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
626 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp361 case ISD::FMAXNUM: in LegalizeOp()
814 case ISD::FMAXNUM: in Expand()
H A DSelectionDAGDumper.cpp185 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
H A DLegalizeFloatTypes.cpp75 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1219 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2281 case ISD::FMAXNUM: in PromoteFloatResult()
2646 case ISD::FMAXNUM: in SoftPromoteHalfResult()
H A DSelectionDAGBuilder.cpp3327 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3330 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect()
3331 Opc = ISD::FMAXNUM; in visitSelect()
3335 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect()
3336 ISD::FMAXNUM : ISD::FMAXIMUM; in visitSelect()
6313 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, in visitIntrinsicCall()
8260 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
H A DLegalizeDAG.cpp3195 case ISD::FMAXNUM: { in ExpandNode()
4003 case ISD::FMAXNUM: in ConvertNodeToLibcall()
4753 case ISD::FMAXNUM: in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp298 ISD::FMAXNUM}, in AMDGPUTargetLowering()
396 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering()
504 case ISD::FMAXNUM: in fnegFoldsIntoOp()
3677 case ISD::FMAXNUM: in inverseMinMax()
3680 return ISD::FMAXNUM; in inverseMinMax()
3795 case ISD::FMAXNUM: in performFNegCombine()
H A DSIISelLowering.cpp616 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom); in SITargetLowering()
622 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, in SITargetLowering()
727 ISD::FMAXNUM, in SITargetLowering()
4716 case ISD::FMAXNUM: in LowerOperation()
6850 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
10063 case ISD::FMAXNUM: in isCanonicalized()
10303 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) { in performFCanonicalizeCombine()
10321 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
10501 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
10676 case ISD::FMAXNUM: in performExtractVectorEltCombine()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DGenericOpcodes.td755 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
778 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp102 setOperationAction(ISD::FMAXNUM, T, Legal); in initializeHVXLowering()
139 setOperationAction(ISD::FMAXNUM, P, Custom); in initializeHVXLowering()
2418 case ISD::FMAXNUM: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1639 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1759 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1808 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp558 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
563 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
568 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
573 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
578 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp795 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp303 ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT, in RISCVTargetLowering()
660 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal); in RISCVTargetLowering()
899 ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM}, in RISCVTargetLowering()
947 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
3582 case ISD::FMAXNUM: in LowerOperation()
7546 case ISD::FMAXNUM: in combineBinOpToReduce()
9030 case ISD::FMAXNUM: in PerformDAGCombine()

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