Searched refs:FGETSIGN (Results 1 – 8 of 8) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 496 FGETSIGN, enumerator
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 271 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
|
| H A D | TargetLowering.cpp | 2476 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits()
2477 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
2484 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); in SimplifyDemandedBits()
|
| H A D | SelectionDAG.cpp | 3525 case ISD::FGETSIGN: in computeKnownBits()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 794 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 486 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 670 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
671 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
32281 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1040 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
|