| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 81 Register ExtSrc; in tryCombineAnyExt() local
84 m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)), in tryCombineAnyExt()
85 m_GSExt(m_Reg(ExtSrc)), in tryCombineAnyExt()
86 m_GZExt(m_Reg(ExtSrc)))))) { in tryCombineAnyExt()
87 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
200 Register ExtSrc; in tryCombineSExt() local
203 m_all_of(m_MInstr(ExtMI), m_any_of(m_GZExt(m_Reg(ExtSrc)), in tryCombineSExt()
204 m_GSExt(m_Reg(ExtSrc)))))) { in tryCombineSExt()
206 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineSExt()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 772 Value *ExtSrc; in instCombineIntrinsic() local
775 match(Src0, m_ZExt(PatternMatch::m_Value(ExtSrc)))) || in instCombineIntrinsic()
777 match(Src0, m_SExt(PatternMatch::m_Value(ExtSrc))))) && in instCombineIntrinsic()
778 ExtSrc->getType()->isIntegerTy(1)) { in instCombineIntrinsic()
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| H A D | AMDGPUISelDAGToDAG.cpp | 1648 SDValue ExtSrc = Op.getOperand(0); in matchZExtFromI32() local
1649 return (ExtSrc.getValueType() == MVT::i32) ? ExtSrc : SDValue(); in matchZExtFromI32()
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| H A D | SIISelLowering.cpp | 9856 SDValue ExtSrc = RHS.getOperand(0); in performOrCombine() local
9857 EVT SrcVT = ExtSrc.getValueType(); in performOrCombine()
9862 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc); in performOrCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 256 Register ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy() local
259 .addDef(ExtSrc) in selectCopy()
264 I.getOperand(1).setReg(ExtSrc); in selectCopy()
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| H A D | X86TargetTransformInfo.cpp | 2595 Type *ExtSrc = Src->getWithNewBitWidth(32); in getCastInstrCost() local
2602 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()
2604 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, in getCastInstrCost()
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| H A D | X86ISelLowering.cpp | 54611 if (SDValue ExtSrc = IsAnyExt64(peekThroughOneUseBitcasts(Src))) in combineScalarToVector() local
54614 DAG.getAnyExtOrTrunc(ExtSrc, DL, MVT::i32))); in combineScalarToVector()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1630 Register ExtSrc; in matchCombineShlOfExtend() local
1631 if (!mi_match(LHS, MRI, m_GAnyExt(m_Reg(ExtSrc))) && in matchCombineShlOfExtend()
1632 !mi_match(LHS, MRI, m_GZExt(m_Reg(ExtSrc))) && in matchCombineShlOfExtend()
1633 !mi_match(LHS, MRI, m_GSExt(m_Reg(ExtSrc)))) in matchCombineShlOfExtend()
1643 LLT SrcTy = MRI.getType(ExtSrc); in matchCombineShlOfExtend()
1654 MatchData.Reg = ExtSrc; in matchCombineShlOfExtend()
1657 unsigned MinLeadingZeros = KB->getKnownZeroes(ExtSrc).countLeadingOnes(); in matchCombineShlOfExtend()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 1952 Value *ExtSrc; in visitCallInst() local
1953 if (match(II->getArgOperand(0), m_OneUse(m_FPExt(m_Value(ExtSrc))))) { in visitCallInst()
1955 Value *NarrowII = Builder.CreateUnaryIntrinsic(IID, ExtSrc, II); in visitCallInst()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3174 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass); in select() local
3176 .addDef(ExtSrc) in select()
3180 I.getOperand(1).setReg(ExtSrc); in select()
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