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Searched refs:ExtOp (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DSCCP.cpp172 Value *ExtOp = Inst.getOperand(0); in simplifyInstsInBlock() local
173 if (isa<Constant>(ExtOp) || InsertedValues.count(ExtOp)) in simplifyInstsInBlock()
175 const ValueLatticeElement &IV = Solver.getLatticeValueFor(ExtOp); in simplifyInstsInBlock()
179 auto *ZExt = new ZExtInst(ExtOp, Inst.getType(), "", &Inst); in simplifyInstsInBlock()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4570 unsigned ExtOp, TruncOp; in PromoteNode() local
4572 ExtOp = ISD::BITCAST; in PromoteNode()
4579 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4583 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
4587 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
4619 unsigned ExtOp, TruncOp; in PromoteNode() local
4622 ExtOp = ISD::BITCAST; in PromoteNode()
4625 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4628 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4674 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
[all …]
H A DDAGCombiner.cpp15707 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
15709 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1535 MachineOperand ExtOp(EV); in insertInitializer() local
1546 .add(ExtOp); in insertInitializer()
1552 .add(ExtOp); in insertInitializer()
1557 .add(ExtOp) in insertInitializer()
1563 .add(ExtOp); in insertInitializer()
1571 .add(ExtOp) in insertInitializer()
1584 .add(ExtOp) in insertInitializer()
1589 .add(ExtOp); in insertInitializer()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSSE.td5034 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5043 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5048 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5078 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
5110 SDNode ExtOp> {
5112 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5116 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
5118 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
5121 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
5123 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
[all …]
H A DX86InstrAVX512.td10244 multiclass AVX512_pmovx_patterns_base<string OpcPrefix, SDNode ExtOp> {
10247 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
10252 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
10255 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
10261 def : Pat<(v32i16 (ExtOp (loadv32i8 addr:$src))),
10265 def : Pat<(v16i32 (ExtOp (loadv16i8 addr:$src))),
10267 def : Pat<(v16i32 (ExtOp (loadv16i16 addr:$src))),
10270 def : Pat<(v8i64 (ExtOp (loadv8i16 addr:$src))),
10273 def : Pat<(v8i64 (ExtOp (loadv8i32 addr:$src))),
10278 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
[all …]
H A DX86ISelLowering.cpp19886 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
19889 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
41438 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
41442 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
41470 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
41474 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
41513 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local
41516 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
54528 unsigned ExtOp = getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineEXTRACT_SUBVECTOR() local
54529 return DAG.getNode(ExtOp, DL, VT, Ext); in combineEXTRACT_SUBVECTOR()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1889 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
1894 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
1955 unsigned ExtOp = IsSigned ? Instruction::SExt : Instruction::ZExt; in getTypeBasedIntrinsicInstrCost() local
1959 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp435 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
436 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
H A DSIISelLowering.cpp10369 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
10371 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
10372 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
10373 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3091 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3104 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3723 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3726 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3729 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3791 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3794 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3797 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3955 IntOp, ExtOp, OpNode>;
3958 IntOp, ExtOp, OpNode>;
[all …]
H A DARMISelLowering.cpp12576 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
12577 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp472 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local
473 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
H A DLegalizerHelper.cpp1910 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local
1912 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); in widenScalarAddSubOverflow()
1986 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local
1987 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); in widenScalarMulo()
1988 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); in widenScalarMulo()
7200 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local
7206 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); in lowerSMULH_UMULH()
7207 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); in lowerSMULH_UMULH()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1499 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1500 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6194 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6195 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
14262 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
14263 if (!ExtOp) in combineBVOfVecSExt()
14266 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6781 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local
6782 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp); in combineINT_TO_FP()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp7270 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
7274 if (ExtOp) in packTBLDVectorList()
7275 TblOps.push_back(ExtOp); in packTBLDVectorList()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19155 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local
19165 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), in performSignExtendInRegCombine()
19166 ExtOp, DAG.getValueType(ExtVT)); in performSignExtendInRegCombine()