| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 288 return Ext1; in getShuffleExtract()
293 return Ext1; in getShuffleExtract()
298 return Index0 > Index1 ? Ext0 : Ext1; in getShuffleExtract()
362 bool HasUseTax = Ext0 == Ext1 ? !Ext0->hasNUses(2) in isExtractExtractCheap()
372 !Ext1->hasOneUse() * Extract1Cost; in isExtractExtractCheap()
504 auto *Ext1 = cast<ExtractElementInst>(I1); in foldExtractExtract() local
523 Ext1 = NewExtract; in foldExtractExtract()
527 foldExtExtCmp(Ext0, Ext1, I); in foldExtractExtract()
529 foldExtExtBinop(Ext0, Ext1, I); in foldExtractExtract()
532 Worklist.push(Ext1); in foldExtractExtract()
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| /llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/ |
| H A D | MsgPack.def | 94 HANDLE_MP_FIX_LEN(0x01, Ext1)
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| /llvm-project-15.0.7/llvm/lib/BinaryFormat/ |
| H A D | MsgPackWriter.cpp | 177 case FixLen::Ext1: in writeExt()
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| H A D | MsgPackReader.cpp | 121 return createExt(Obj, FixLen::Ext1); in read()
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| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | lookahead.ll | 220 …al_uses(double* %A, double *%B, double *%C, double *%D, double *%S, double *%Ext1, double *%Ext2) {
291 store double %A1, double *%Ext1, align 8
310 …dget(double* %A, double *%B, double *%C, double *%D, double *%S, double *%Ext1, double *%Ext2, dou…
385 store double %A1, double *%Ext1, align 8
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9243 SDValue Ext1 = Ext.getValue(1); in LowerVectorExtend() local
9247 Ext1 = DAG.getNode(N->getOpcode(), DL, MVT::v8i32, Ext1); in LowerVectorExtend()
13136 SDValue Ext1 = Mul.getOperand(1); in PerformVQDMULHCombine() local
13138 Ext1.getOpcode() != ISD::SIGN_EXTEND) in PerformVQDMULHCombine()
13143 if (Ext1.getOperand(0).getValueType() != VecVT || in PerformVQDMULHCombine()
16990 SDValue Ext1 = in PerformVECREDUCE_ADDCombine() local
16995 Ext0, Ext1); in PerformVECREDUCE_ADDCombine()
16999 Ext0.getValue(1), Ext1.getValue(1)); in PerformVECREDUCE_ADDCombine()
18953 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
18959 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12736 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
12742 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
12744 !areExtDoubled(cast<Instruction>(Ext1)) || in areExtractExts()
12879 auto Ext1 = cast<Instruction>(I->getOperand(0)); in shouldSinkOperands() local
12882 Ops.push_back(&Ext1->getOperandUse(0)); in shouldSinkOperands()
13933 SDValue Ext1 = Op1.getOperand(0); in performUADDVCombine() local
13935 Ext1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVCombine()
13936 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVCombine()
13945 (Ext1.getConstantOperandVal(1) != 0 && in performUADDVCombine()
16781 const SDValue Ext1 = in performSignExtendSetCCCombine() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2804 auto Ext1 = B.buildFPExt(S32, Src1, Flags); in legalizeFPow() local
2807 .addUse(Ext1.getReg(0)) in legalizeFPow()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14418 SDValue Ext1 = FirstInput.getOperand(0); in DAGCombineBuildVector() local
14420 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in DAGCombineBuildVector()
14424 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1)); in DAGCombineBuildVector()
14428 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
14429 Ext1.getOperand(0) != Ext2.getOperand(0)) in DAGCombineBuildVector()
14442 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 11307 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); in tryToFoldExtendSelectLoad() local
11309 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); in tryToFoldExtendSelectLoad()
11930 SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); in foldSextSetcc() local
11931 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
19753 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); in scalarizeExtractedBinop() local
19754 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 43618 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
43620 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
43642 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in scalarizeExtEltFP() local
43646 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
54537 SDValue Ext1 = extractSubVector(InVec.getOperand(1), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
54539 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
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