| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 286 return Ext0; in getShuffleExtract()
295 return Ext0; in getShuffleExtract()
298 return Index0 > Index1 ? Ext0 : Ext1; in getShuffleExtract()
316 Type *ScalarTy = Ext0->getType(); in isExtractExtractCheap()
362 bool HasUseTax = Ext0 == Ext1 ? !Ext0->hasNUses(2) in isExtractExtractCheap()
503 auto *Ext0 = cast<ExtractElementInst>(I0); in foldExtractExtract() local
520 if (ExtractToChange == Ext0) in foldExtractExtract()
521 Ext0 = NewExtract; in foldExtractExtract()
527 foldExtExtCmp(Ext0, Ext1, I); in foldExtractExtract()
529 foldExtExtBinop(Ext0, Ext1, I); in foldExtractExtract()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10172 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10184 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10188 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
13135 SDValue Ext0 = Mul.getOperand(0); in PerformVQDMULHCombine() local
13137 if (Ext0.getOpcode() != ISD::SIGN_EXTEND || in PerformVQDMULHCombine()
13140 EVT VecVT = Ext0.getOperand(0).getValueType(); in PerformVQDMULHCombine()
13158 DAG.getNode(ISD::ANY_EXTEND, DL, ExtVecVT, Ext0.getOperand(0)); in PerformVQDMULHCombine()
13175 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
16987 SDValue Ext0 = in PerformVECREDUCE_ADDCombine() local
16995 Ext0, Ext1); in PerformVECREDUCE_ADDCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2803 auto Ext0 = B.buildFPExt(S32, Log, Flags); in legalizeFPow() local
2806 .addUse(Ext0.getReg(0)) in legalizeFPow()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13932 SDValue Ext0 = Op0.getOperand(0); in performUADDVCombine() local
13934 if (Ext0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVCombine()
13936 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVCombine()
13940 if (Ext0.getOperand(0).getValueType().getVectorNumElements() != in performUADDVCombine()
13943 if ((Ext0.getConstantOperandVal(1) != 0 && in performUADDVCombine()
13946 Ext0.getConstantOperandVal(1) != VT.getVectorNumElements())) in performUADDVCombine()
13950 return DAG.getNode(Opcode, SDLoc(A), VT, Ext0.getOperand(0)); in performUADDVCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41436 SDValue Ext0 = in SimplifyDemandedVectorEltsForTargetNode() local
41439 TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0, Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode()
43616 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
43620 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
43639 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in scalarizeExtEltFP() local
43646 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
54536 SDValue Ext0 = extractSubVector(InVec.getOperand(0), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
54539 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
54552 SDValue Ext0 = in combineEXTRACT_SUBVECTOR() local
54554 return DAG.getNode(InOpcode, DL, VT, Ext0); in combineEXTRACT_SUBVECTOR()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 11929 SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); in foldSextSetcc() local
11931 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
19752 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Index); in scalarizeExtractedBinop() local
19754 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
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