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Searched refs:Enc (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td17 class Wi<bits<16> Enc, string n> : Register<n> {
18 let HWEncoding = Enc;
24 class Ri<bits<16> Enc, string n, list<Register> subregs>
26 let HWEncoding = Enc;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td29 class MipsReg<bits<16> Enc, string n> : Register<n> {
30 let HWEncoding = Enc;
36 let HWEncoding = Enc;
41 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
45 : MipsRegWithSubRegs<Enc, n, subregs> {
50 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
54 : MipsRegWithSubRegs<Enc, n, subregs> {
60 : MipsRegWithSubRegs<Enc, n, subregs> {
67 : MipsRegWithSubRegs<Enc, n, subregs> {
73 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Bitstream/
H A DBitCodes.h36 unsigned Enc : 3; // The encoding to use. variable
52 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
61 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp458 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getSDWASrcEncoding() local
459 if (Enc != ~0U && Enc != 255) { in getSDWASrcEncoding()
460 Op = Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
492 uint64_t Enc = MRI.getEncodingValue(Reg); in getAVOperandEncoding() local
507 Enc |= 512; in getAVOperandEncoding()
509 Op = Enc; in getAVOperandEncoding()
577 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getMachineOpValueCommon() local
578 if (Enc != ~0U) { in getMachineOpValueCommon()
579 Op = Enc; in getMachineOpValueCommon()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td13 class SparcReg<bits<16> Enc, string n> : Register<n> {
14 let HWEncoding = Enc;
18 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
19 let HWEncoding = Enc;
32 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
41 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
160 if (Enc != -1) in LowerARMMachineInstrToMCInst()
161 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
H A DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td14 class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
16 let HWEncoding = Enc;
20 class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
22 let HWEncoding = Enc;
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DTargetInfo.cpp10171 return Enc < rhs.Enc; in operator <()
10556 Enc += '('; in appendRecordType()
10559 Enc += "){"; in appendRecordType()
10589 Enc += '}'; in appendRecordType()
10606 Enc += "e("; in appendEnumType()
10609 Enc += "){"; in appendEnumType()
10632 Enc += '}'; in appendEnumType()
10718 Enc += ')'; in appendPointerType()
10734 Enc += ':'; in appendArrayType()
10739 Enc += ')'; in appendArrayType()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td14 class CSKYReg<bits<6> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{5 - 0} = Enc;
19 class CSKYFReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4 - 0} = Enc;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp430 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
437 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && in addEntryWithFlags()
438 Enc != X86Local::EVEX) { in addEntryWithFlags()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td14 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{4-0} = Enc;
19 class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4-0} = Enc;
45 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
48 let HWEncoding{4-0} = Enc;
/llvm-project-15.0.7/llvm/include/llvm/Transforms/IPO/
H A DAttributor.h448 IRPosition() : Enc(nullptr, ENC_VALUE) { verify(); }
534 return Enc == RHS.Enc && RHS.CBContext == CBContext;
783 Enc.setFromOpaqueValue(Ptr);
797 Enc = {&AnchorVal, ENC_FLOATING_FUNCTION};
799 Enc = {&AnchorVal, ENC_VALUE};
803 Enc = {&AnchorVal, ENC_VALUE};
807 Enc = {&AnchorVal, ENC_RETURNED_VALUE};
810 Enc = {&AnchorVal, ENC_VALUE};
845 Enc = {&U, ENC_CALL_SITE_ARGUMENT_USE};
875 return reinterpret_cast<Use *>(Enc.getPointer());
[all …]
/llvm-project-15.0.7/clang-tools-extra/clangd/
H A DSourceCode.cpp104 static size_t measureUnits(llvm::StringRef U8, int Units, OffsetEncoding Enc, in measureUnits() argument
110 switch (Enc) { in measureUnits()
143 auto *Enc = Context::current().get(kCurrentOffsetEncoding); in lspEncoding() local
144 return Enc ? *Enc : OffsetEncoding::UTF16; in lspEncoding()
H A DProtocol.cpp1407 llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, OffsetEncoding Enc) { in operator <<() argument
1408 return OS << toString(Enc); in operator <<()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5898 uint64_t Enc = (32 - *MaybeImmed) & 0x1f; in selectShiftA_32() local
5899 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_32()
5907 uint64_t Enc = 31 - *MaybeImmed; in selectShiftB_32() local
5908 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_32()
5916 uint64_t Enc = (64 - *MaybeImmed) & 0x3f; in selectShiftA_64() local
5917 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_64()
5925 uint64_t Enc = 63 - *MaybeImmed; in selectShiftB_64() local
5926 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_64()
6717 uint64_t Enc = AArch64_AM::encodeLogicalImmediate(CstVal, 32); in renderLogicalImm32() local
6718 MIB.addImm(Enc); in renderLogicalImm32()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Demangle/
H A DItaniumDemangle.h2590 char Enc[2]; // Encoding member
2599 : Enc{E[0], E[1]}, Kind{K}, Flag{F}, Prec{P}, Name{N} {} in OperatorInfo()
2603 return *this < Other.Enc;
2606 return Enc[0] < Peek[0] || (Enc[0] == Peek[0] && Enc[1] < Peek[1]);
2609 return Enc[0] == Peek[0] && Enc[1] == Peek[1];
/llvm-project-15.0.7/libcxxabi/src/demangle/
H A DItaniumDemangle.h2590 char Enc[2]; // Encoding member
2599 : Enc{E[0], E[1]}, Kind{K}, Flag{F}, Prec{P}, Name{N} {} in OperatorInfo()
2603 return *this < Other.Enc;
2606 return Enc[0] < Peek[0] || (Enc[0] == Peek[0] && Enc[1] < Peek[1]);
2609 return Enc[0] == Peek[0] && Enc[1] == Peek[1];
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1191 unsigned Enc = 0; in getDefaultCustomOperandEncoding() local
1195 Enc |= Op.encode(Op.Default); in getDefaultCustomOperandEncoding()
1197 return Enc; in getDefaultCustomOperandEncoding()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2631 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands() local
2632 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
2638 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands() local
2639 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
4460 unsigned Enc, unsigned Reg) { in insertNoDuplicates() argument
4461 Regs.emplace_back(Enc, Reg); in insertNoDuplicates()
4463 if (J->first == Enc) { in insertNoDuplicates()
4467 if (J->first < Enc) in insertNoDuplicates()
5490 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm() local
8778 unsigned Enc = Inst.getOperand(2).getImm(); in processInstruction() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
17 let HWEncoding = Enc;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInsertWaitcnts.cpp1282 unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); in generateWaitcnt() local
1284 BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); in generateWaitcnt()
H A DBUFInstructions.td2641 class MUBUF_Real_Base_vi <bits<7> op, MUBUF_Pseudo ps, int Enc,
2645 SIMCInstr<ps.PseudoInstr, Enc>,
2889 class MTBUF_Real_Base_vi <bits<4> op, MTBUF_Pseudo ps, int Enc> :
2892 SIMCInstr<ps.PseudoInstr, Enc> {
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2211 if (unsigned Enc = dwarf::getAttributeEncoding(Token.stringValue())) { in parseDIExpression() local
2213 Elements.push_back(Enc); in parseDIExpression()
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DAttributor.cpp992 assert(!Enc.getOpaqueValue() && in verify()

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