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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpredicates.ll12 br i1 %cmp0, label %IF, label %ENDIF
16 br label %ENDIF
18 ENDIF:
35 br label %ENDIF
39 br label %ENDIF
41 ENDIF:
66 br label %ENDIF
68 ENDIF:
94 br label %ENDIF
98 br label %ENDIF
[all …]
H A Dselectcc-opt.ll19 br i1 %6, label %IF, label %ENDIF
24 br label %ENDIF
26 ENDIF:
47 br i1 %6, label %ENDIF, label %IF
52 br label %ENDIF
54 ENDIF:
H A Dlegalizedag-bug-expand-setcc.ll17 br i1 %0, label %IF, label %ENDIF
21 br label %ENDIF
23 ENDIF:
H A Dschedule-if.ll14 br i1 %7, label %ENDIF, label %ELSE
25 br i1 %15, label %IF13, label %ENDIF
27 ENDIF: ; preds = %IF13, %ELSE, %main_body
43 br label %ENDIF
H A Dpredicate-dp4.ll11 br i1 %3, label %IF, label %ENDIF
15 br label %ENDIF
17 ENDIF: ; preds = %IF, %main_body
H A Djump-address.ll17 br i1 %7, label %ENDIF, label %ELSE
28 br i1 %15, label %IF13, label %ENDIF
30 ENDIF: ; preds = %IF13, %ELSE, %main_body
47 br label %ENDIF
H A Dmultilevel-break.ll24 ; OPT-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]]
27 ; OPT-NEXT: [[TMP5]] = phi i32 [ [[TMP47]], [[ENDIF]] ], [ undef, [[LOOP]] ]
28 ; OPT-NEXT: [[TMP6:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
42 ; OPT: ENDIF:
82 ; GCN-NEXT: ; %bb.5: ; %ENDIF
96 LOOP.outer: ; preds = %ENDIF, %main_body
97 %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
100 LOOP: ; preds = %ENDIF, %LOOP.outer
101 %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
103 br i1 %tmp48, label %ENDIF, label %IF
[all …]
H A Dfcmp.ll28 br i1 %0, label %IF, label %ENDIF
33 br label %ENDIF
35 ENDIF:
H A Dearly-if-convert.ll115 ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
128 ; GCN: [[ENDIF]]:
158 ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
162 ; GCN: [[ENDIF]]:
183 ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
187 ; GCN: [[ENDIF]]:
270 ; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
274 ; GCN: [[ENDIF]]:
405 ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
410 ; GCN: [[ENDIF]]:
[all …]
H A Duniform-crash.ll13 br i1 %0, label %IF, label %ENDIF
17 br label %ENDIF
19 ENDIF: ; preds = %IF, %main_body
H A Dschedule-if-2.ll47 br label %ENDIF
58 br i1 %43, label %IF23, label %ENDIF
60 ENDIF: ; preds = %IF23, %ELSE, %IF
87 br label %ENDIF
H A Dvtx-fetch-branch.ll3 ; This tests for a bug where vertex fetch clauses right before an ENDIF
4 ; instruction where being emitted after the ENDIF. We were using ALU_POP_AFTER
H A Dschedule-fs-loop.ll38 br label %ENDIF
41 br i1 %tmp30, label %ENDIF, label %ELSE17
43 ENDIF: ; preds = %ELSE17, %ELSE, %IF
76 br label %ENDIF
H A Dschedule-fs-loop-nested-if.ll38 br label %ENDIF
41 br i1 %tmp30, label %ENDIF, label %ELSE17
43 ENDIF: ; preds = %ELSE17, %ELSE, %IF
76 br label %ENDIF
H A Dsgpr-copy.ll17 br i1 %tmp25, label %ENDIF, label %ELSE
21 br label %ENDIF
114 br i1 %tmp76, label %IF, label %ENDIF
124 br label %ENDIF
136 IF25: ; preds = %ENDIF
147 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ]
186 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]
187 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ]
188 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]
196 br i1 %tmp33, label %IF, label %ENDIF
[all …]
H A Dbug-vopc-commute.ll15 IF57: ; preds = %ENDIF
19 ENDIF56: ; preds = %IF57, %ENDIF
H A Dschedule-vs-if-nested-loop.ll17 br i1 %10, label %LOOP, label %ENDIF
19 ENDIF: ; preds = %ENDIF16, %LOOP, %main_body
109 br i1 %85, label %ENDIF, label %ENDIF16
119 br i1 %92, label %ENDIF, label %ENDIF19
H A Dstructurize.ll38 ; === diamond_false block plus implicit ENDIF
40 ; === Branch instruction (ENDIF):
/llvm-project-15.0.7/llvm/cmake/platforms/
H A DiOS.cmake17 ENDIF()
29 ENDIF()
37 ENDIF()
46 ENDIF()
55 ENDIF()
64 ENDIF()
73 ENDIF()
82 ENDIF()
91 ENDIF()
102 ENDIF()
H A DAndroid.cmake17 ENDIF()
21 ENDIF()
/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/
H A Dnested-loop-order.ll19 ; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow
24 br i1 %tmp22, label %ENDLOOP, label %ENDIF
38 ; CHECK: ENDIF:
40 ENDIF: ; preds = %LOOP
49 IF29: ; preds = %ENDIF
61 ENDIF28: ; preds = %ENDIF
/llvm-project-15.0.7/llvm/test/tools/llvm-ml/
H A Dmacro_function.asm64 ENDIF
73 ENDIF
94 ENDIF
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A DPhiNoEliminate.ll11 ; CHECK-NEXT: br i1 [[C:%.*]], label [[THEN:%.*]], label [[ENDIF:%.*]]
14 ; CHECK-NEXT: br label [[ENDIF]]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/AMDGPU/
H A Daddressing-modes.ll11 ; CHECK-NEXT: br i1 [[TMP0]], label [[ENDIF:%.*]], label [[IF:%.*]]
15 ; CHECK-NEXT: br label [[ENDIF]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dvector.ll23 ; CHECK-NEXT: br i1 [[CMP0]], label [[IF:%.*]], label [[ENDIF:%.*]]
28 ; CHECK-NEXT: br label [[ENDIF]]

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