1c581611eSMatt Arsenault; RUN: llc < %s -march=r600 -mcpu=redwood -r600-ir-structurize=0 | FileCheck %s 245bb48eaSTom Stellard; Test case for a crash in the AMDILCFGStructurizer from a CFG like this: 345bb48eaSTom Stellard; 445bb48eaSTom Stellard; entry 545bb48eaSTom Stellard; / \ 645bb48eaSTom Stellard; diamond_head branch_from 745bb48eaSTom Stellard; / \ | 845bb48eaSTom Stellard; diamond_false diamond_true 945bb48eaSTom Stellard; \ / 1045bb48eaSTom Stellard; done 1145bb48eaSTom Stellard; 1245bb48eaSTom Stellard; When the diamond_true branch had more than 100 instructions. 1345bb48eaSTom Stellard; 1445bb48eaSTom Stellard; 1545bb48eaSTom Stellard 1645bb48eaSTom Stellard; CHECK-LABEL: {{^}}branch_into_diamond: 1745bb48eaSTom Stellard; === entry block: 1845bb48eaSTom Stellard; CHECK: ALU_PUSH_BEFORE 1945bb48eaSTom Stellard; === Branch instruction (IF): 2045bb48eaSTom Stellard; CHECK: JUMP 2145bb48eaSTom Stellard ; === branch_from block 2245bb48eaSTom Stellard ; CHECK: ALU 2345bb48eaSTom Stellard ; === Duplicated diamond_true block (There can be more than one ALU clause): 2445bb48eaSTom Stellard ; === XXX: We should be able to optimize this so the basic block is not 2545bb48eaSTom Stellard ; === duplicated. See comments in 2645bb48eaSTom Stellard ; === AMDGPUCFGStructurizer::improveSimpleJumpintoIf() 2745bb48eaSTom Stellard ; CHECK: ALU 2845bb48eaSTom Stellard; === Branch instruction (ELSE): 2945bb48eaSTom Stellard; CHECK: ELSE 3045bb48eaSTom Stellard ; === diamond_head block: 3145bb48eaSTom Stellard ; CHECK: ALU_PUSH_BEFORE 3245bb48eaSTom Stellard ; === Branch instruction (IF): 3345bb48eaSTom Stellard ; CHECK: JUMP 3445bb48eaSTom Stellard ; === diamond_true block (There can be more than one ALU clause): 3545bb48eaSTom Stellard ; ALU 3645bb48eaSTom Stellard ; === Branch instruction (ELSE): 3745bb48eaSTom Stellard ; CHECK: ELSE 3845bb48eaSTom Stellard ; === diamond_false block plus implicit ENDIF 3945bb48eaSTom Stellard ; CHECK: ALU_POP_AFTER 4045bb48eaSTom Stellard; === Branch instruction (ENDIF): 4145bb48eaSTom Stellard; CHECK: POP 4245bb48eaSTom Stellard; === done block: 4345bb48eaSTom Stellard; CHECK: ALU 4445bb48eaSTom Stellard; CHECK: MEM_RAT_CACHELESS 4545bb48eaSTom Stellard; CHECK: CF_END 4645bb48eaSTom Stellard 4745bb48eaSTom Stellard 48*3dbeefa9SMatt Arsenaultdefine amdgpu_kernel void @branch_into_diamond(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 4945bb48eaSTom Stellardentry: 5045bb48eaSTom Stellard%0 = icmp ne i32 %a, 0 5145bb48eaSTom Stellard br i1 %0, label %diamond_head, label %branch_from 5245bb48eaSTom Stellard 5345bb48eaSTom Stellarddiamond_head: 5445bb48eaSTom Stellard %1 = icmp ne i32 %a, 1 5545bb48eaSTom Stellard br i1 %1, label %diamond_true, label %diamond_false 5645bb48eaSTom Stellard 5745bb48eaSTom Stellardbranch_from: 5845bb48eaSTom Stellard %2 = add i32 %a, 1 5945bb48eaSTom Stellard br label %diamond_true 6045bb48eaSTom Stellard 6145bb48eaSTom Stellarddiamond_false: 6245bb48eaSTom Stellard %3 = add i32 %a, 2 6345bb48eaSTom Stellard br label %done 6445bb48eaSTom Stellard 6545bb48eaSTom Stellarddiamond_true: 6645bb48eaSTom Stellard %4 = phi i32 [%2, %branch_from], [%a, %diamond_head] 6745bb48eaSTom Stellard ; This block needs to be > 100 ISA instructions to hit the bug, 6845bb48eaSTom Stellard ; so we'll use udiv instructions. 6945bb48eaSTom Stellard %div0 = udiv i32 %a, %b 7045bb48eaSTom Stellard %div1 = udiv i32 %div0, %4 7145bb48eaSTom Stellard %div2 = udiv i32 %div1, 11 7245bb48eaSTom Stellard %div3 = udiv i32 %div2, %a 7345bb48eaSTom Stellard %div4 = udiv i32 %div3, %b 7445bb48eaSTom Stellard %div5 = udiv i32 %div4, %c 7545bb48eaSTom Stellard %div6 = udiv i32 %div5, %div0 7645bb48eaSTom Stellard %div7 = udiv i32 %div6, %div1 7745bb48eaSTom Stellard br label %done 7845bb48eaSTom Stellard 7945bb48eaSTom Stellarddone: 8045bb48eaSTom Stellard %5 = phi i32 [%3, %diamond_false], [%div7, %diamond_true] 8145bb48eaSTom Stellard store i32 %5, i32 addrspace(1)* %out 8245bb48eaSTom Stellard ret void 8345bb48eaSTom Stellard} 84