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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td148 let Defs = [EFLAGS] in {
193 } // Defs = [EFLAGS]
196 let Defs = [EFLAGS] in {
279 } // Defs = [EFLAGS]
390 } // Defs = [EFLAGS]
534 } // Defs = [EFLAGS]
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
927 // and use EFLAGS.
1038 let Uses = [EFLAGS], Defs = [EFLAGS] in {
1101 } // Uses = [EFLAGS], Defs = [EFLAGS]
[all …]
H A DX86InstrCMovSetCC.td17 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
44 timm:$cond, EFLAGS))]>, TB, OpSize16;
49 timm:$cond, EFLAGS))]>, TB, OpSize32;
54 timm:$cond, EFLAGS))]>, TB;
76 let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
79 [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
83 [(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
85 } // Uses = [EFLAGS]
[all …]
H A DX86InstrKL.td19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
26 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
32 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
39 Defs = [EFLAGS] in {
42 [(set VR128:$dst, EFLAGS,
48 [(set VR128:$dst, EFLAGS,
54 [(set VR128:$dst, EFLAGS,
60 [(set VR128:$dst, EFLAGS,
69 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86InstrCompiler.td38 // sub / add which can clobber EFLAGS.
56 // sub / add which can clobber EFLAGS.
84 let Defs = [EFLAGS] in {
263 Defs = [R10, R11, EFLAGS] in {
348 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC],
505 let Defs = [EAX, ECX, EFLAGS, DF],
518 let Defs = [RAX, EFLAGS, DF],
669 let isCodeGenOnly = 1, Defs = [EFLAGS] in
880 let Defs = [AL, EFLAGS], Uses = [AL] in
884 let Defs = [AX, EFLAGS], Uses = [AX] in
[all …]
H A DX86FlagsCopyLowering.cpp388 MI.getOperand(0).getReg() == X86::EFLAGS) in runOnMachineFunction()
485 while (TestMBB->isLiveIn(X86::EFLAGS) && !TestMBB->pred_empty() && in runOnMachineFunction()
517 return MI.findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
581 if (MI.findRegisterDefOperand(X86::EFLAGS)) { in runOnMachineFunction()
631 assert(MI.findRegisterDefOperand(X86::EFLAGS) && in runOnMachineFunction()
659 if (SuccMBB->isLiveIn(X86::EFLAGS) && in runOnMachineFunction()
693 SuccMBB->removeLiveIn(X86::EFLAGS); in runOnMachineFunction()
720 (MI.getOperand(0).getReg() == X86::EFLAGS || in runOnMachineFunction()
721 MI.getOperand(1).getReg() == X86::EFLAGS)) { in runOnMachineFunction()
750 if (MI.findRegisterDefOperand(X86::EFLAGS)) in collectCondsInRegs()
[all …]
H A DX86InstrInfo.td38 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1490 let Defs = [EFLAGS] in {
1540 } // Defs = [EFLAGS]
2082 } // Defs = [EFLAGS]
2302 let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
2320 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2335 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2340 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2345 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2747 } // HasTBM, EFLAGS
[all …]
H A DX86CmovConversion.cpp349 if (I.definesRegister(X86::EFLAGS)) { in collectCmovCandidates()
577 if (MI->killsRegister(X86::EFLAGS)) in checkEFLAGSLive()
587 if (I->readsRegister(X86::EFLAGS)) in checkEFLAGSLive()
589 if (I->definesRegister(X86::EFLAGS)) in checkEFLAGSLive()
595 if (Succ->isLiveIn(X86::EFLAGS)) in checkEFLAGSLive()
688 FalseMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
689 SinkMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
H A DX86SpeculativeLoadHardening.cpp487 ZeroI->findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
737 bool LiveEFLAGS = Succ.isLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
739 CheckingMBB.addLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
1077 assert(!MBB.isLiveIn(X86::EFLAGS) && in tracePredStateThroughIndirectBranches()
1227 if (MI.killsRegister(X86::EFLAGS, &TRI)) in isEFLAGSLive()
1233 return MBB.isLiveIn(X86::EFLAGS); in isEFLAGSLive()
1541 ShiftI->addRegisterDead(X86::EFLAGS, TRI); in mergePredStateIntoSP()
1546 OrI->addRegisterDead(X86::EFLAGS, TRI); in mergePredStateIntoSP()
1566 ShiftI->addRegisterDead(X86::EFLAGS, TRI); in extractPredStateFromSP()
1744 OrI->addRegisterDead(X86::EFLAGS, TRI); in hardenLoadAddr()
[all …]
H A DX86FixupSetCC.cpp72 if (MI.definesRegister(X86::EFLAGS)) in runOnMachineFunction()
97 if (FlagsDefMI->readsRegister(X86::EFLAGS)) in runOnMachineFunction()
H A DX86InstrTSX.td42 let Defs = [EFLAGS] in
44 "xtest", [(set EFLAGS, (X86xtest))]>, PS, Requires<[HasRTM]>;
H A DX86InstrFPStack.td123 // Clobbers EFLAGS due to OR instruction used internally.
125 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in {
434 cc, EFLAGS))]>;
438 cc, EFLAGS))]>;
442 cc, EFLAGS))]>,
447 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
456 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
664 let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
666 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
669 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
[all …]
H A DX86FixupLEAs.cpp439 if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI)) in searchALUInst()
536 NewMI1->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
541 NewMI2->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
568 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) != in optTwoAddrLEA()
708 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstructionForSlowLEA()
760 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstrForSlow3OpLEA()
H A DX86InstrControl.td73 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
78 [(X86brcond bb:$dst, timm:$cond, EFLAGS)]>;
311 // rather than barriers, and they use EFLAGS.
314 let Uses = [ESP, EFLAGS, SSP] in {
435 // rather than barriers, and they use EFLAGS.
438 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86LoadValueInjectionRetHardening.cpp101 ->addRegisterDead(X86::EFLAGS, TRI); in runOnMachineFunction()
H A DX86InstrShiftRotate.td15 let Defs = [EFLAGS] in {
340 } // Uses = [CL, EFLAGS]
342 let Uses = [EFLAGS] in {
359 } // Uses = [EFLAGS]
370 } // Uses = [CL, EFLAGS]
372 let Uses = [EFLAGS] in {
389 } // Uses = [EFLAGS]
394 let Uses = [EFLAGS] in {
430 } // Uses = [EFLAGS]
452 } // Uses = [CL, EFLAGS]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dhandle-move.ll11 ; 144B -> 180B: DIV32r %4, implicit-def %eax, implicit dead %edx, implicit dead %EFLAGS, implicit k…
28 ; 144B -> 180B: DIV32r %4, implicit dead %eax, implicit-def %edx, implicit dead %EFLAGS, implicit k…
61 ; Move EFLAGS dead def across another def:
62 ; handleMove 208B -> 36B: %edx = MOV32r0 implicit dead %EFLAGS
63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208…
H A Di686-win-shrink-wrapping.ll8 ; Check that we do not use a basic block that has EFLAGS as live-in
18 ; this point, EFLAGS is live.
H A D2012-01-16-mfence-nosse-flags.ll14 ; clobbers EFLAGS.
H A Dpeep-test-2.ll5 ; EFLAGS value from the incl, however it can't be known whether the add
H A Dvaargs.ll21 ; Check that [EFLAGS] hasn't been pulled in.
H A Dmisched-crash.ll6 ; Hoisting the last use requires trimming the EFLAGS live range to the second.
H A Dpre-ra-sched.ll10 ; CHECK: Interfering reg EFLAGS
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DSnippetGeneratorTest.cpp74 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS); in TEST_F()
76 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS); in TEST_F()
99 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS); in TEST_F()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Ddependency-breaking-sbb-1.s5 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/
H A Ddependency-breaking-sbb-1.s7 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend

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