Lines Matching refs:EFLAGS
38 // sub / add which can clobber EFLAGS.
39 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
56 // sub / add which can clobber EFLAGS.
57 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
72 let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in {
78 (implicit EFLAGS)]>;
81 let usesCustomInserter = 1, Defs = [EFLAGS] in {
84 let Defs = [EFLAGS] in {
91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
113 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
130 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
151 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
157 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
167 let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {
263 Defs = [R10, R11, EFLAGS] in {
292 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
310 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
348 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC],
461 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
481 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
505 let Defs = [EAX, ECX, EFLAGS, DF],
518 let Defs = [RAX, EFLAGS, DF],
537 EFLAGS)))]>;
540 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
552 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
592 } // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]
594 def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
598 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
600 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
602 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
604 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
606 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
609 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
611 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
613 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
615 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
617 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
621 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
623 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
625 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
627 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
629 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
631 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
634 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
636 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
638 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
640 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
642 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
644 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
648 def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
650 def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
652 def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
654 def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
656 def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
658 def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
669 let isCodeGenOnly = 1, Defs = [EFLAGS] in
686 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
694 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
701 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
709 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
717 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;
726 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,
734 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,
742 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,
750 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;
757 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,
765 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,
773 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,
796 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
800 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>,
804 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>,
808 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>,
812 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>,
817 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>,
821 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>,
825 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>,
829 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>,
855 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
859 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>,
863 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>,
867 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>,
880 let Defs = [AL, EFLAGS], Uses = [AL] in
884 let Defs = [AX, EFLAGS], Uses = [AX] in
888 let Defs = [EAX, EFLAGS], Uses = [EAX] in
892 let Defs = [RAX, EFLAGS], Uses = [RAX] in
899 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
907 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
934 let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
946 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX],
985 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1,
1466 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1854 // amount could affect EFLAGS results, but that does not matter because we are
1990 // EFLAGS-defining Patterns