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Searched refs:DstRB (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp634 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() local
636 if (!DstRB) in getInstrMapping()
637 DstRB = SrcRB; in getInstrMapping()
639 SrcRB = DstRB; in getInstrMapping()
642 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
645 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
646 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
659 const RegisterBank &DstRB = in getInstrMapping() local
664 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
665 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
H A DAArch64InstructionSelector.cpp3072 if (DstRB.getID() != SrcRB.getID()) { in select()
3078 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
3110 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
4083 getRegClassForTypeOnBank(ScalarTy, DstRB, true); in emitExtractVectorElt()
4184 const RegisterBank &DstRB = in selectSplitVectorUnmerge() local
5458 const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI); in tryOptBuildVecToSubregToReg() local
5459 if (EltRB != DstRB) in tryOptBuildVecToSubregToReg()
5472 getRegClassForTypeOnBank(MRI.getType(Dst), DstRB); in tryOptBuildVecToSubregToReg()
6804 const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg); in fixupPHIOpBanks() local
6814 if (RB != DstRB) { in fixupPHIOpBanks()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp288 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
289 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
1928 const RegisterBank *DstRB; in selectG_TRUNC() local
1932 DstRB = SrcRB; in selectG_TRUNC()
1934 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
1935 if (SrcRB != DstRB) in selectG_TRUNC()
1947 TRI.getRegClassForSizeOnBank(DstSize, *DstRB); in selectG_TRUNC()
2206 if (DstRB->getID() == AMDGPU::VCCRegBankID) { in selectG_CONSTANT()
2275 if (DstRB->getID() != AMDGPU::SGPRRegBankID || in selectG_FNEG()
2320 if (DstRB->getID() != AMDGPU::SGPRRegBankID || in selectG_FABS()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp721 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() local
724 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
730 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
742 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
850 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext() local
853 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
859 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
868 if (DstRB.getID() != X86::GPRRegBankID) in selectAnyext()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1011 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1014 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()