Lines Matching refs:DstRB
280 const RegisterBank &DstRB, LLT ScalarTy,
2643 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
2644 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2657 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
3069 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
3072 if (DstRB.getID() != SrcRB.getID()) { in select()
3078 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
3079 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select()
3110 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
3120 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB); in select()
3403 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
3404 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select()
4071 Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy, in emitExtractVectorElt() argument
4083 getRegClassForTypeOnBank(ScalarTy, DstRB, true); in emitExtractVectorElt()
4159 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectExtractElt() local
4160 MachineInstr *Extract = emitExtractVectorElt(DstReg, DstRB, NarrowTy, SrcReg, in selectExtractElt()
4184 const RegisterBank &DstRB = in selectSplitVectorUnmerge() local
4189 emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB); in selectSplitVectorUnmerge()
5458 const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI); in tryOptBuildVecToSubregToReg() local
5459 if (EltRB != DstRB) in tryOptBuildVecToSubregToReg()
5472 getRegClassForTypeOnBank(MRI.getType(Dst), DstRB); in tryOptBuildVecToSubregToReg()
6804 const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg); in fixupPHIOpBanks() local
6805 assert(DstRB && "Expected PHI dst to have regbank assigned"); in fixupPHIOpBanks()
6814 if (RB != DstRB) { in fixupPHIOpBanks()
6827 MRI.setRegBank(Copy.getReg(0), *DstRB); in fixupPHIOpBanks()