287   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_AND_OR_XOR()  local
288   if (DstRB->getID() != AMDGPU::SGPRRegBankID &&  in selectG_AND_OR_XOR()
289       DstRB->getID() != AMDGPU::VCCRegBankID)  in selectG_AND_OR_XOR()
292   bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&  in selectG_AND_OR_XOR()
314   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_ADD_SUB()  local
315   const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_ADD_SUB()
1237   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectGroupStaticSize()  local
1238   unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ?  in selectGroupStaticSize()
1928   const RegisterBank *DstRB;  in selectG_TRUNC()  local
1932     DstRB = SrcRB;  in selectG_TRUNC()
1934     DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_TRUNC()
1935     if (SrcRB != DstRB)  in selectG_TRUNC()
1939   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_TRUNC()
1947       TRI.getRegClassForSizeOnBank(DstSize, *DstRB);  in selectG_TRUNC()
2202   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_CONSTANT()  local
2203   const bool IsSgpr = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_CONSTANT()
2206   if (DstRB->getID() == AMDGPU::VCCRegBankID) {  in selectG_CONSTANT()
2274   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FNEG()  local
2275   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FNEG()
2319   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FABS()  local
2320   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FABS()
2536   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_GLOBAL_VALUE()  local
2537   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_GLOBAL_VALUE()
2555   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_PTRMASK()  local
2558   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_PTRMASK()
2559   if (DstRB != SrcRB) // Should only happen for hand written MIR.  in selectG_PTRMASK()
2584   const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB);  in selectG_PTRMASK()
2691   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_EXTRACT_VECTOR_ELT()  local
2703       TRI.getRegClassForTypeOnBank(DstTy, *DstRB);  in selectG_EXTRACT_VECTOR_ELT()
2882   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_SHUFFLE_VECTOR()  local
2883   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_SHUFFLE_VECTOR()
3408   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectWaveAddress()  local
3409   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectWaveAddress()