Home
last modified time | relevance | path

Searched refs:CondCodes (Results 1 – 25 of 43) sorted by relevance

12

/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.h31 enum CondCodes { enum
69 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
70 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
71 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
H A DAVRInstrInfo.cpp201 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { in getBrCond()
224 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { in getCondFromBranchOpc()
247 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { in getOppositeCondition()
329 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in analyzeBranch()
391 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
426 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
479 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
137 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
187 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); in MoveCopyOutOfITBlock()
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
226 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
244 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); in InsertITInstructions()
H A DARMLoadStoreOptimizer.cpp489 ARMCC::CondCodes Pred, in UpdateBaseRegUses()
630 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
908 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1297 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLSMultiple()
1493 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLoadStore()
1631 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSDouble()
1801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in FixInvalidRegPairOp()
1881 ARMCC::CondCodes CurrPred = ARMCC::AL; in LoadStoreMultipleOpti()
2174 ARMCC::CondCodes &Pred, bool &isT2);
2259 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { in CanFormLdStDWord()
[all …]
H A DARMBaseInstrInfo.h165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() in getPredicate()
541 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
782 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
798 ARMCC::CondCodes Pred, Register PredReg,
805 ARMCC::CondCodes Pred, Register PredReg,
H A DThumbRegisterInfo.h42 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DThumb2InstrInfo.h77 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
391 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
393 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL}; in getComparePreds()
575 ARMCC::CondCodes Cond, in insertComparison()
H A DMLxExpansionPass.cpp281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2SizeReduction.cpp187 bool is2Addr, ARMCC::CondCodes Pred,
334 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
804 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
897 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DARMBaseRegisterInfo.h216 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMBaseInstrInfo.cpp215 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); in convertToThreeAddress()
551 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in reverseBranchCondition()
595 CC += ARMCondCodeToString((ARMCC::CondCodes)Op.getImm()); in createMIROperandComment()
637 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
638 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
2251 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in getInstrPredicate()
2274 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2852 inline static ARMCC::CondCodes getCmpToAddCondition(ARMCC::CondCodes CC) { in getCmpToAddCondition()
3151 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> in optimizeCompareInstr()
3172 ARMCC::CondCodes CC; in optimizeCompareInstr()
[all …]
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
850 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
851 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
H A DThumb2InstrInfo.cpp74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
291 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
766 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI, in getITInstrPredicate()
H A DMVETPAndVPTOptimisationsPass.cpp574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode()
576 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
593 ARMCC::CondCodes ExpectedCode = GetCondCode(Cond); in IsVPNOTEquivalent()
/llvm-project-15.0.7/llvm/lib/Target/ARM/Utils/
H A DARMBaseInfo.h30 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
48 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
71 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { in getSwappedCondition()
146 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
219 MSP430CC::CondCodes BranchCode = in analyzeBranch()
220 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
H A DMSP430.h22 enum CondCodes { enum
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparc.h40 enum CondCodes { enum
94 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
H A DSparcInstrInfo.cpp81 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
300 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTX.h27 enum CondCodes { enum
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp961 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
972 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS) in printMandatoryRestrictedPredicateOperand()
982 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
990 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryInvertedPredicateOperand()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp200 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp924 auto CondCodes = enum_seq_inclusive(X86::CondCode::COND_O, in generateInstructionVariants() local
927 Choices.reserve(CondCodes.size()); in generateInstructionVariants()
928 for (int CondCode : CondCodes) in generateInstructionVariants()

12