| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 190 bool widenCondCommon(Value *Cond0, Value *Cond1, Instruction *InsertPt,
252 bool isWideningCondProfitable(Value *Cond0, Value *Cond1, bool InvertCond) { in isWideningCondProfitable() argument
254 return widenCondCommon(Cond0, Cond1, /*InsertPt=*/nullptr, ResultUnused, in isWideningCondProfitable()
502 bool GuardWideningImpl::widenCondCommon(Value *Cond0, Value *Cond1, in widenCondCommon() argument
512 if (match(Cond0, m_ICmp(Pred0, m_Value(LHS), m_ConstantInt(RHS0))) && in widenCondCommon()
531 ConstantInt::get(Cond0->getContext(), NewRHSAP); in widenCondCommon()
544 parseRangeChecks(Cond0, Checks) && parseRangeChecks(Cond1, Checks) && in widenCondCommon()
566 makeAvailableAt(Cond0, InsertPt); in widenCondCommon()
570 Result = BinaryOperator::CreateAnd(Cond0, Cond1, "wide.chk", InsertPt); in widenCondCommon()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | select_fmf.ll | 6 ; select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
64 ; select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 475 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0); in generateCondForPow() local
476 return BBBuilder.CreateOr(Cond0, Cond); in generateCondForPow()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroSplit.cpp | 1294 ConstantInt *Cond0 = TryResolveConstant(CondCmp->getOperand(0)); in simplifyTerminatorLeadingToRet() local
1296 if (!Cond0 || !Cond1) in simplifyTerminatorLeadingToRet()
1303 CondCmp->getPredicate(), Cond0, Cond1, DL)); in simplifyTerminatorLeadingToRet()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10292 SDValue Cond0 = N0.getOperand(0); in foldVSelectToSignBitSplatMask() local
10295 if (VT != Cond0.getValueType()) in foldVSelectToSignBitSplatMask()
10311 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
10319 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
10330 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
10378 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
10383 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, in visitSELECT()
10391 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
10396 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1, in visitSELECT()
10451 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); in visitSELECT() local
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44826 SDValue Cond0 = Cond.getOperand(0); in combineSelect() local
44849 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
44853 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
44858 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
44876 Cond0 == InnerSetCC.getOperand(0) && in combineSelect()
44887 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
|