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Searched refs:CombineTo (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp591 return TLO.CombineTo(Op, Z); in ShrinkDemandedOp()
1414 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1717 return TLO.CombineTo( in SimplifyDemandedBits()
1738 return TLO.CombineTo( in SimplifyDemandedBits()
1761 return TLO.CombineTo( in SimplifyDemandedBits()
1860 return TLO.CombineTo( in SimplifyDemandedBits()
1940 return TLO.CombineTo( in SimplifyDemandedBits()
2176 return TLO.CombineTo(Op, in SimplifyDemandedBits()
2402 return TLO.CombineTo( in SimplifyDemandedBits()
2490 return TLO.CombineTo(Op, in SimplifyDemandedBits()
[all …]
H A DDAGCombiner.cpp2989 return CombineTo( in visitADDO()
3296 return CombineTo( in visitADDCARRYLike()
6241 CombineTo(N, Zext); in visitAND()
11573 CombineTo(N, NewValue); in CombineExtLoad()
11646 CombineTo(N, And); in CombineZExtLogicopShiftLoad()
12084 CombineTo(N, And); in visitSIGN_EXTEND()
12369 CombineTo(N, And); in visitZERO_EXTEND()
13085 CombineTo(N, ExtLoad); in visitSIGN_EXTEND_INREG()
13102 CombineTo(N, ExtLoad); in visitSIGN_EXTEND_INREG()
15842 CombineTo(N, ExtLoad); in visitFP_EXTEND()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3553 bool CombineTo(SDValue O, SDValue N) { in CombineTo() function
3827 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3828 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3829 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp40973 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41015 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41022 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41041 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41075 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41114 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41559 return TLO.CombineTo( in SimplifyDemandedVectorEltsForTargetNode()
41669 return TLO.CombineTo( in SimplifyDemandedBitsForTargetNode()
41782 return TLO.CombineTo( in SimplifyDemandedBitsForTargetNode()
51680 DCI.CombineTo(N, Setcc); in combineSext()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp14062 DCI.CombineTo(N, Res, false); in PerformMULCombine()
14332 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14359 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14376 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14397 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
15874 DCI.CombineTo(N, NewResults); in TryCombineBaseUpdate()
16158 DCI.CombineTo(N, NewResults); in PerformMVEVLDCombine()
16243 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
19945 return TLO.CombineTo(Op, NewOp); in targetShrinkDemandedConstant()
19993 return TLO.CombineTo( in SimplifyDemandedBitsForTargetNode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1826 return TLO.CombineTo(Op, New); in optimizeLogicalImm()
17519 DCI.CombineTo(LD, NewResults); in performPostLD1Combine()
17922 DCI.CombineTo(N, NewResults); in performNEONPostLDSTCombine()
17923 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in performNEONPostLDSTCombine()
18243 DCI.CombineTo(N, BR, false); in performBRCONDCombine()
18436 DCI.CombineTo(Generic, SDValue(N, 0)); in performFlagSettingCombine()
19257 DCI.CombineTo(N, ExtLoad); in performSignExtendInRegCombine()
19258 DCI.CombineTo(Src.getNode(), ExtLoad, ExtLoad.getValue(1)); in performSignExtendInRegCombine()
19421 DCI.CombineTo(N, ExtLoad); in performFPExtendCombine()
19422 DCI.CombineTo(N0.getNode(), in performFPExtendCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6210 DCI.CombineTo(N0.getNode(), TruncSelect); in combineZERO_EXTEND()
6547 DCI.CombineTo(N, ESLoad); in combineVECTOR_SHUFFLE()
6551 DCI.CombineTo(Load.getNode(), ESLoad, ESLoad.getValue(1)); in combineVECTOR_SHUFFLE()
6817 DCI.CombineTo(N, ResVal); in combineBSWAP()
6821 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); in combineBSWAP()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8845 return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1)); in PerformDAGCombine()
8850 return DCI.CombineTo(N, Lo, Hi); in PerformDAGCombine()
8862 return DCI.CombineTo(N, Lo, Hi); in PerformDAGCombine()
8881 return DCI.CombineTo(N, Lo, NewHi); in PerformDAGCombine()
8886 return DCI.CombineTo(N, Lo, NewHi); in PerformDAGCombine()
9052 DCI.CombineTo(N, Res); in PerformDAGCombine()
9473 return TLO.CombineTo(Op, NewOp); in targetShrinkDemandedConstant()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2900 DCI.CombineTo(N, BC, NewLoad.getValue(1)); in performLoadCombine()
3385 DCI.CombineTo(N, Lo, Hi); in performMulLoHiCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15348 DCI.CombineTo(Bitcast2, FloatLoad); in PerformDAGCombine()
15349 DCI.CombineTo(Bitcast, FloatLoad2); in PerformDAGCombine()
15486 DCI.CombineTo(N, Perm, TF); in PerformDAGCombine()
15632 DCI.CombineTo(N, ResVal); in PerformDAGCombine()
15636 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4672 DCI.CombineTo(N, Val, AddTo); in PerformANDCombine()