| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 138 Register CmpReg = AndCC->getReg(); in optimizeVcndVcmpPair() local
140 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
142 CmpReg = AndCC->getReg(); in optimizeVcndVcmpPair()
148 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
267 LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr; in optimizeVcndVcmpPair()
269 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
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| H A D | AMDGPURegisterBankInfo.cpp | 902 auto CmpReg = B.buildICmp(CmpInst::ICMP_EQ, S1, CurrentLaneParts[i], in executeInWaterfallLoop() local
904 MRI.setRegBank(CmpReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
907 CondReg = CmpReg; in executeInWaterfallLoop()
909 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 426 Register CmpReg = MI.getOperand(2).getReg(); in processSwitches() local
430 MRI.hasOneDef(CmpReg)); in processSwitches()
435 SwitchRegToMBB[CmpReg][Val] = CBr->getOperand(1).getMBB(); in processSwitches()
445 NextMBB->front().getOperand(2).getReg() != CmpReg)) in processSwitches()
446 DefaultMBBs[CmpReg] = NextMBB; in processSwitches()
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| H A D | SPIRVModuleAnalysis.cpp | 343 Register CmpReg = MI.getOperand(0).getReg(); in processSwitches() local
347 CBr->getOperand(0).getReg() == CmpReg); in processSwitches()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 405 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock() local
406 if (any_of(MI->implicit_operands(), [CmpReg](MachineOperand &O) { in optimizeBlock()
408 O.getReg() != CmpReg; in optimizeBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 473 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
476 CmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in LowerFPToInt()
491 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
502 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
503 CmpReg = AndReg; in LowerFPToInt()
506 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg); in LowerFPToInt()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2208 Register CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpRHSReg, in X86FastEmitSSESelect() local
2221 unsigned MovReg = fastEmitInst_rrrr(MovOpcode, VR128X, RHSReg, CmpReg, in X86FastEmitSSESelect()
2241 Register CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpRHSReg, in X86FastEmitSSESelect() local
2244 CmpReg); in X86FastEmitSSESelect()
2263 Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpRHSReg, CC); in X86FastEmitSSESelect() local
2264 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect()
2265 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); in X86FastEmitSSESelect()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1290 Register CmpReg = getRegForValue(BI->getCondition()); in SelectBranch() local
1291 if (CmpReg == 0) return false; in SelectBranch()
1301 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1304 .addReg(CmpReg) in SelectBranch()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11708 unsigned CmpReg = Incr2Reg; in EmitPartwordAtomicBinary() local
11718 CmpReg = incr; in EmitPartwordAtomicBinary()
11721 .addReg(CmpReg) in EmitPartwordAtomicBinary()
12365 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); in EmitInstrWithCustomInserter() local
12367 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg) in EmitInstrWithCustomInserter()
12372 .addReg(CmpReg) in EmitInstrWithCustomInserter()
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