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Searched refs:CPSR (Results 1 – 25 of 49) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcopy-cpsr.ll5 ; In the ARM backend, most compares are glued to their uses so CPSR can't
8 ; copying CPSR.
14 ; CPSR is used twice).
15 ; + We want both chains to write CPSR post-split (so that the copy can't be
H A Davoid-cpsr-rmw.ll3 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
4 ; dependency) when it isn't dependent on last CPSR defining instruction.
21 ; Avoid partial CPSR dependency via loop backedge.
54 ; Allow partial CPSR dependency when code size is the priority.
H A Dload_store_opt_clobber_cpsr.mir3 # Make sure bb.0 isn't transformed: it would incorrectly clobber CPSR.
H A Dcse-call.ll5 ; Don't CSE a cmp across a call that clobbers CPSR.
H A Dcrash-O0.ll7 ; This function would crash RegAllocFast because it tried to spill %CPSR.
H A Dcopy-by-struct-i32.ll5 ; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand.
H A Dinterrupt-attr.ll13 ; Also need special function return setting pc and CPSR simultaneously.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp257 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
305 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
385 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
819 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
883 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
911 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
988 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
1003 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
1049 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); in ReduceMBB()
1104 if (BundleMI->killsRegister(ARM::CPSR)) in ReduceMBB()
[all …]
H A DARMInstrThumb.td419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1006 let isCommutable = 1, Uses = [CPSR] in
1103 let isCompare = 1, Defs = [CPSR] in {
1118 } // isCompare = 1, Defs = [CPSR]
1121 let isCompare = 1, Defs = [CPSR] in {
1150 } // isCompare = 1, Defs = [CPSR]
1228 let Defs = [CPSR] in
1309 let Uses = [CPSR] in
1355 /// instruction modifies the CPSR register.
[all …]
H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMBaseInstrInfo.cpp762 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
981 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
984 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2276 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
3116 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3260 if (Succ->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3267 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
3279 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
4396 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
5583 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
[all …]
H A DARMFastISel.cpp252 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
253 *CPSR = true; in DefinesOptionalPredicate()
290 bool CPSR = false; in AddOptionalDefs() local
291 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
292 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1254 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1277 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1480 .addImm(ARMPred).addReg(ARM::CPSR); in SelectCmp()
1664 .addReg(ARM::CPSR); in SelectSelect()
1672 .addReg(ARM::CPSR); in SelectSelect()
[all …]
H A DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1863 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1866 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1879 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1933 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
3696 let Uses = [CPSR] in
3704 let Defs = [CPSR] in {
3864 // CPSR and the implicit def of CPSR is not needed.
4989 Defs = [CPSR] in {
5800 let Defs = [CPSR] in
[all …]
H A DARMInstrThumb2.td726 /// changed to modify CPSR.
1025 let Defs = [CPSR], Uses = [CPSR] in {
1031 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
1041 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
1055 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
2406 // CPSR and the implicit def of CPSR is not needed.
2713 let Uses = [CPSR] in {
2881 /// changed to modify CPSR.
4464 let Defs = [CPSR] in
4500 let Defs = [CPSR] in
[all …]
H A DARM.td390 /// Some instructions update CPSR partially, which can add false dependency for
392 /// mapped to a separate physical register. Avoid partial CPSR update for these
395 /// that partially update CPSR and add false dependency on the previous
396 /// CPSR setting instruction.
399 "Avoid CPSR partial update for OOO execution">;
401 /// Disable +1 predication cost for instructions updating CPSR.
403 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
407 "Disable +1 predication cost for instructions updating CPSR">;
H A DThumb2ITBlockPass.cpp173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARMInstructionSelector.cpp602 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
796 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1136 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMExpandPseudoInsts.cpp1118 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1242 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1783 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1807 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1900 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1906 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1928 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2263 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2465 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2664 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
H A DARMAsmPrinter.cpp1775 .addReg(ARM::CPSR) in emitInstruction()
1831 .addReg(ARM::CPSR) in emitInstruction()
1962 .addReg(ARM::CPSR) in emitInstruction()
1981 .addReg(ARM::CPSR) in emitInstruction()
1996 .addReg(ARM::CPSR) in emitInstruction()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-2011-04-21-CPSRBug.ll3 ; CPSR is not allocatable so fast allocatable wouldn't mark them killed.
H A Darm64-2011-03-09-CPSRSpill.ll3 ; Can't copy or spill / restore CPSR.
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp180 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
246 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dv8_IT_6.ll3 ; Narrow tORR cannot be predicated and set CPSR at the same time!
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.

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