Home
last modified time | relevance | path

Searched refs:CONV (Results 1 – 25 of 148) sorted by relevance

123456

/llvm-project-15.0.7/mlir/test/Dialect/SparseTensor/
H A Dsparse_reshape.mlir24 // CHECK-CONV: call @getNextF64
25 // CHECK-CONV: scf.condition(%13)
26 // CHECK-CONV: } do {
32 // CHECK-CONV: call @addEltF64
33 // CHECK-CONV: scf.yield
34 // CHECK-CONV: }
63 // CHECK-CONV: call @getNextF64
65 // CHECK-CONV: } do {
71 // CHECK-CONV: call @addEltF64
72 // CHECK-CONV: scf.yield
[all …]
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dconvert-debugloc.ll33 ; CONV: DW_TAG_compile_unit
38 ; CONV-NOT: DW_AT
43 ; CONV-NOT: DW_AT
44 ; CONV: DW_TAG_base_type
45 ; CONV: DW_TAG_base_type
46 ; CONV: DW_TAG_subprogram
56 ; CONV: NULL
57 ; CONV: DW_TAG_base_type
59 ; CONV: DW_TAG_base_type
61 ; CONV: DW_TAG_base_type
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_select_cmp.ll7 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32
8 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 109
24 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32
43 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32
62 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32
101 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 0
102 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[CONV]]
120 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 0
121 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[CONV]]
139 ; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[CONV]]
[all …]
H A Dtrunc_select.ll108 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i16
109 ; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[CONV]]
110 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]
124 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i16
125 ; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[CONV]]
126 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dicmp-and-shift.ll10 ; CHECK-NEXT: ret i32 [[CONV]]
36 ; CHECK-NEXT: ret i32 [[CONV]]
62 ; CHECK-NEXT: ret i32 [[CONV]]
88 ; CHECK-NEXT: ret i32 [[CONV]]
129 ; CHECK-NEXT: ret i32 [[CONV]]
154 ; CHECK-NEXT: ret i32 [[CONV]]
180 ; CHECK-NEXT: ret i32 [[CONV]]
206 ; CHECK-NEXT: ret i32 [[CONV]]
232 ; CHECK-NEXT: ret i32 [[CONV]]
260 ; CHECK-NEXT: ret i32 [[CONV]]
[all …]
H A Dexp2-1.ll22 ; LDEXP16-NEXT: [[CONV:%.*]] = sitofp i32 [[X:%.*]] to double
23 ; LDEXP16-NEXT: [[RET:%.*]] = call double @exp2(double [[CONV]])
31 ; NOLDEXP-NEXT: [[CONV:%.*]] = sitofp i32 [[X:%.*]] to double
32 ; NOLDEXP-NEXT: [[RET:%.*]] = call double @exp2(double [[CONV]])
56 ; NOLDEXP-NEXT: [[CONV:%.*]] = sitofp i16 [[X:%.*]] to double
82 ; NOLDEXP-NEXT: [[CONV:%.*]] = sitofp i8 [[X:%.*]] to double
97 ; LDEXP16-NEXT: [[CONV:%.*]] = sitofp i32 [[X:%.*]] to float
102 ; NOLDEXPF-NEXT: [[CONV:%.*]] = sitofp i32 [[X:%.*]] to float
107 ; NOLDEXP-NEXT: [[CONV:%.*]] = sitofp i32 [[X:%.*]] to float
213 ; NOLDEXP-NEXT: [[CONV:%.*]] = uitofp i8 [[X:%.*]] to float
[all …]
H A Dstrcmp-memcmp.ll17 ; CHECK-NEXT: ret i32 [[CONV]]
34 ; CHECK-NEXT: ret i32 [[CONV]]
49 ; CHECK-NEXT: ret i32 [[CONV]]
64 ; CHECK-NEXT: ret i32 [[CONV]]
79 ; CHECK-NEXT: ret i32 [[CONV]]
94 ; CHECK-NEXT: ret i32 [[CONV]]
123 ; CHECK-NEXT: ret i32 [[CONV]]
138 ; CHECK-NEXT: ret i32 [[CONV]]
154 ; CHECK-NEXT: ret i32 [[CONV]]
171 ; CHECK-NEXT: ret i32 [[CONV]]
[all …]
H A Ddouble-float-shrink-1.ll28 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
51 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
75 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
98 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
122 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
145 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
168 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
192 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
215 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
228 ; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double
[all …]
H A D2011-05-28-swapmulsub.ll9 ; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -2
10 ; CHECK-NEXT: ret i16 [[CONV]]
28 ; CHECK-NEXT: [[CONV:%.*]] = shl i16 [[SUBA_TR]], 2
29 ; CHECK-NEXT: ret i16 [[CONV]]
50 ; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -28
51 ; CHECK-NEXT: ret i16 [[CONV]]
H A Dselect-cmp-cttz-ctlz.ll158 ; CHECK-NEXT: [[CONV:%.*]] = zext i16 [[CT]] to i64
159 ; CHECK-NEXT: ret i64 [[CONV]]
171 ; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[CT]] to i64
172 ; CHECK-NEXT: ret i64 [[CONV]]
224 ; CHECK-NEXT: ret i16 [[CONV]]
302 ; CHECK-NEXT: ret i64 [[CONV]]
315 ; CHECK-NEXT: ret i16 [[CONV]]
481 ; CHECK-NEXT: ret i64 [[CONV]]
496 ; CHECK-NEXT: ret i64 [[CONV]]
511 ; CHECK-NEXT: ret i16 [[CONV]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/X86/
H A Dfptosisat.ll6 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
19 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
32 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
45 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
58 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i64
71 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i64
84 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i32
97 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
110 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
123 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dsigned-div-rem.ll15 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
16 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 128
35 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
36 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], -128
55 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[X:%.*]] to i32
56 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 255
76 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], -255
167 ; CHECK-NEXT: ret i32 [[CONV]]
188 ; CHECK-NEXT: ret i32 [[CONV]]
209 ; CHECK-NEXT: ret i32 [[CONV]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dtwo-shifts-by-sext.ll32 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[LEN:%.*]] to i32
33 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[VAL:%.*]], [[CONV]]
34 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
53 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[LEN:%.*]] to i32
55 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
76 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[LEN:%.*]] to i32
77 ; CHECK-NEXT: call void @use_int32(i32 [[CONV]])
79 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
103 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[LEN:%.*]] to i32
104 ; CHECK-NEXT: call void @use_int32(i32 [[CONV]])
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/ARM/
H A Dfptosisat.ll8 ; CHECK-BASE-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
31 ; CHECK-BASE-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
54 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
67 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
80 ; CHECK-BASE-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i64
104 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i64
117 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i32
130 ; CHECK-BASE-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
153 ; CHECK-BASE-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
176 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/AArch64/
H A Dfptosisat.ll19 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
32 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
45 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i32
70 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i64
83 ; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[IN:%.*]] to i32
96 ; CHECK-FP-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
114 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
127 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i32
140 ; CHECK-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i32
226 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[IN:%.*]] to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/IPConstantProp/
H A DPR16052.ll22 ; IS__CGSCC____-NEXT: [[CONV:%.*]] = sext i32 undef to i64
23 ; IS__CGSCC____-NEXT: [[DIV:%.*]] = sdiv i64 8, [[CONV]]
40 ; IS__TUNIT____-NEXT: [[CONV:%.*]] = sext i32 [[ARG]] to i64
41 ; IS__TUNIT____-NEXT: [[DIV:%.*]] = sdiv i64 8, [[CONV]]
48 ; IS__CGSCC____-NEXT: [[CONV:%.*]] = sext i32 [[ARG]] to i64
49 ; IS__CGSCC____-NEXT: [[DIV:%.*]] = sdiv i64 8, [[CONV]]
71 ; IS__CGSCC____-NEXT: [[CONV:%.*]] = sext i32 undef to i64
72 ; IS__CGSCC____-NEXT: [[ADD:%.*]] = add i64 42, [[CONV]]
/llvm-project-15.0.7/llvm/test/Demangle/
H A Dms-options.test2 ; RUN: llvm-undname --no-calling-convention < %s | FileCheck %s --check-prefix=CHECK-NO-CALLING-CONV
11 ; CHECK-NO-CALLING-CONV: public: virtual int MyClass::func(int, int)
20 ; CHECK-NO-CALLING-CONV: int (*array2d)[10]
29 ; CHECK-NO-CALLING-CONV: int (*abc::a)[10]
38 ; CHECK-NO-CALLING-CONV: unsigned char *x
/llvm-project-15.0.7/clang/test/utils/update_cc_test_checks/Inputs/
H A Dgenerated-funcs-regex.c.expected22 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23 // CHECK-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
34 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
35 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
H A Dmangled_names.c.expected13 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
14 // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
32 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
33 // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
H A Dmangled_names.c.funcsig.expected14 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
15 // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
34 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
35 // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
/llvm-project-15.0.7/llvm/test/Transforms/ExpandMemCmp/X86/
H A Dmemcmp-x32.ll320 ; X32-NEXT: ret i32 [[CONV]]
347 ; X32-NEXT: ret i32 [[CONV]]
365 ; X32-NEXT: ret i32 [[CONV]]
392 ; X32-NEXT: ret i32 [[CONV]]
421 ; X32-NEXT: ret i32 [[CONV]]
450 ; X32-NEXT: ret i32 [[CONV]]
477 ; X32-NEXT: ret i32 [[CONV]]
504 ; X32-NEXT: ret i32 [[CONV]]
517 ; X32-NEXT: ret i32 [[CONV]]
530 ; X32-NEXT: ret i32 [[CONV]]
[all …]
H A Dmemcmp.ll527 ; X64-NEXT: ret i32 [[CONV]]
558 ; X64_1LD-NEXT: ret i32 [[CONV]]
578 ; X64_2LD-NEXT: ret i32 [[CONV]]
596 ; X64-NEXT: ret i32 [[CONV]]
627 ; X64_1LD-NEXT: ret i32 [[CONV]]
647 ; X64_2LD-NEXT: ret i32 [[CONV]]
680 ; X64_1LD-NEXT: ret i32 [[CONV]]
702 ; X64_2LD-NEXT: ret i32 [[CONV]]
735 ; X64_1LD-NEXT: ret i32 [[CONV]]
828 ; X64-NEXT: ret i32 [[CONV]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dnamedop_conversion.mlir7 …// CHECK-DAG: %[[CONV:.+]] = linalg.depthwise_conv_2d_nhwc_hwc {dilations = dense<1> : tensor<2xi6…
8 // CHECK: %[[OUT:.+]] = tensor.expand_shape %[[CONV]] {{\[\[}}0], [1], [2], [3, 4]]
20 …// CHECK-DAG: %[[CONV:.+]] = linalg.depthwise_conv_2d_nhwc_hwc_q {dilations = dense<1> : tensor<2x…
21 // CHECK: %[[OUT:.+]] = tensor.expand_shape %[[CONV]] {{\[\[}}0], [1], [2], [3, 4]]
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dsigned.ll27 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i16
28 ; CHECK-NEXT: ret i16 [[CONV]]
40 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i16
41 ; CHECK-NEXT: ret i16 [[CONV]]
53 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i16
54 ; CHECK-NEXT: ret i16 [[CONV]]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dmatrix-type-operators.m19 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
26 // CHECK-NEXT: [[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]]
46 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
53 // CHECK-NEXT: [[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]]

123456