| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | ComparisonCategories.cpp | 185 using CCVT = ComparisonCategoryResult; in getResultString() typedef
187 case CCVT::Equal: in getResultString()
189 case CCVT::Equivalent: in getResultString()
191 case CCVT::Less: in getResultString()
193 case CCVT::Greater: in getResultString()
195 case CCVT::Unordered: in getResultString()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4306 EVT CCVT = getSetCCResultType(VT); in visitSDIV() local
4325 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), in visitSDIV()
4384 EVT CCVT = getSetCCResultType(VT); in visitSDIVLike() local
4422 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ); in visitSDIVLike()
4423 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ); in visitSDIVLike()
4433 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT); in visitSDIVLike()
4454 EVT CCVT = getSetCCResultType(VT); in visitUDIV() local
4469 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), in visitUDIV()
4563 EVT CCVT = getSetCCResultType(VT); in visitREM() local
4576 SDValue EqualsNeg1 = DAG.getSetCC(DL, CCVT, F0, N1, ISD::SETEQ); in visitREM()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 7182 EVT CCVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntrinsicCall() local
7186 if (!TLI.shouldExpandGetActiveLaneMask(CCVT, ElementVT)) { in visitIntrinsicCall()
7192 auto VecTy = CCVT.changeVectorElementType(ElementVT); in visitIntrinsicCall()
7205 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall()
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| H A D | LegalizeDAG.cpp | 3706 EVT CCVT = getSetCCResultType(CmpVT); in ExpandNode() local
3707 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags()); in ExpandNode()
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| H A D | TargetLowering.cpp | 6642 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSqrtInputTest() local
6654 return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); in getSqrtInputTest()
6657 return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); in getSqrtInputTest()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1936 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in LowerUDIVREM() local
1938 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
1945 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
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| H A D | SIISelLowering.cpp | 4895 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize); in lowerICMPIntrinsic() local
4897 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic()
4899 if (VT.bitsEq(CCVT)) in lowerICMPIntrinsic()
4926 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize); in lowerFCMPIntrinsic() local
4927 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic()
4929 if (VT.bitsEq(CCVT)) in lowerFCMPIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 8855 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSqrtInputTest() local
8857 return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); in getSqrtInputTest()
18673 EVT CCVT = N0.getValueType(); in performVSelectCombine() local
18715 CCVT.getVectorElementCount() != ElementCount::getFixed(1) || in performVSelectCombine()
18716 CCVT.getVectorElementType() != MVT::i1) in performVSelectCombine()
18772 EVT CCVT = SrcVT.changeVectorElementTypeToInteger(); in performSelectCombine() local
18777 if (CCVT.getSizeInBits() != ResVT.getSizeInBits()) in performSelectCombine()
18791 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine()
18794 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0); in performSelectCombine()
18795 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask); in performSelectCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44146 EVT CCVT = VT.changeVectorElementType(MVT::i1); in combineToExtendBoolVectorInReg() local
44147 Vec = DAG.getSetCC(DL, CCVT, Vec, BitMask, ISD::SETEQ); in combineToExtendBoolVectorInReg()
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