Home
last modified time | relevance | path

Searched refs:BitMask (Results 1 – 25 of 34) sorted by relevance

12

/llvm-project-15.0.7/llvm/test/Transforms/LowerTypeTests/
H A Dexport-inline.ll35 ; SUMMARY-X86-NEXT: BitMask: 0
39 ; SUMMARY-ARM-NEXT: BitMask: 0
48 ; SUMMARY-X86-NEXT: BitMask: 0
52 ; SUMMARY-ARM-NEXT: BitMask: 0
H A Dexport-bytearray.ll42 ; SUMMARY-X86-NEXT: BitMask: 0
46 ; SUMMARY-ARM-NEXT: BitMask: 2
55 ; SUMMARY-X86-NEXT: BitMask: 0
59 ; SUMMARY-ARM-NEXT: BitMask: 1
H A Dexport-allones.ll163 ; SUMMARY-X86-NEXT: BitMask: 0
167 ; SUMMARY-ARM-NEXT: BitMask: 0
176 ; SUMMARY-X86-NEXT: BitMask: 0
180 ; SUMMARY-ARM-NEXT: BitMask: 0
H A Dexport-icall.ll70 ; SUMMARY-NEXT: BitMask: 0
79 ; SUMMARY-NEXT: BitMask: 0
/llvm-project-15.0.7/llvm/test/Transforms/WholeProgramDevirt/
H A Dexport-single-impl.ll11 ; SUMMARY-NEXT: BitMask: 0
24 ; SUMMARY-NEXT: BitMask: 0
37 ; SUMMARY-NEXT: BitMask: 0
50 ; SUMMARY-NEXT: BitMask: 0
H A Dexport-unique-ret-val.ll13 ; SUMMARY-NEXT: BitMask: 0
31 ; SUMMARY-NEXT: BitMask: 0
H A Dbranch-funnel.ll17 ; SUMMARY-NEXT: BitMask: 0
30 ; SUMMARY-NEXT: BitMask: 0
43 ; SUMMARY-NEXT: BitMask: 0
H A Dexport-uniform-ret-val.ll13 ; SUMMARY-NEXT: BitMask: 0
H A Dexport-vcp.ll16 ; SUMMARY-NEXT: BitMask: 0
36 ; SUMMARY-NEXT: BitMask: 0
H A Dimport-indir.ll40 ; SUMMARY-NEXT: BitMask: 0
/llvm-project-15.0.7/llvm/test/Transforms/LowerTypeTests/Inputs/
H A Dimport.yaml21 BitMask: 64
28 BitMask: 128
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DBitTracker.h39 struct BitMask;
287 struct BitTracker::BitMask { struct
288 BitMask() = default;
289 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {} in BitMask() function
317 RegisterCell &insert(const RegisterCell &RC, const BitMask &M); argument
318 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
465 virtual BitMask mask(Register Reg, unsigned Sub) const;
H A DBitTracker.cpp215 const BitMask &M) { in insert()
235 BT::RegisterCell BT::RegisterCell::extract(const BitMask &M) const { in extract()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
690 RegisterCell Res = RegisterCell::ref(A1).extract(BT::BitMask(B, Last)); in eXTR()
703 Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1)); in eINS()
707 BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const { in mask()
711 return BitMask(0, W-1); in mask()
752 Res.insert(Src, BitMask(0, WS-1)); in evaluate()
1002 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub); in subst()
1003 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub); in subst()
H A DHexagonBitTracker.h39 BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
H A DHexagonBitTracker.cpp89 BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const { in mask()
101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate()
371 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate()
726 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); in evaluate()
/llvm-project-15.0.7/clang/lib/AST/Interp/
H A DIntegral.h143 const T BitMask = (T(1) << T(TruncBits)) - 1;
145 const T ExtMask = ~BitMask;
146 return Integral((V & BitMask) | (Signed && (V & SignBit) ? ExtMask : 0));
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DLowerTypeTests.cpp452 Constant *BitMask; member
567 Value *BitMask = B.CreateShl(ConstantInt::get(BitsType, 1), BitIndex); in createMaskedBitTest() local
568 Value *MaskedBits = B.CreateAnd(Bits, BitMask); in createMaskedBitTest()
665 B.CreateAnd(Byte, ConstantExpr::getPtrToInt(TIL.BitMask, Int8Ty)); in createBitSetTest()
925 ExportGlobal("bit_mask", TIL.BitMask); in exportTypeId()
927 return &TTRes.BitMask; in exportTypeId()
1000 TIL.BitMask = ImportConstant("bit_mask", TTRes.BitMask, 8, Int8PtrTy); in importTypeId()
1136 TIL.BitMask = BAI->MaskGlobal; in lowerTypeTestCalls()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp343 uint64_t BitMask = ~BypassType->getBitMask(); in insertOperandRuntimeCheck() local
344 Value *AndV = Builder.CreateAnd(OrV, BitMask); in insertOperandRuntimeCheck()
H A DSimplifyCFG.cpp5692 APInt BitMask = APInt::getZero(MinCaseVal->getBitWidth()); in foldSwitchToSelect() local
5694 BitMask |= (Case->getValue() - MinCaseVal->getValue()); in foldSwitchToSelect()
5698 if (BitMask.countPopulation() == Log2_32(CaseCount)) { in foldSwitchToSelect()
5701 Value *And = Builder.CreateAnd(Condition, ~BitMask, "switch.and"); in foldSwitchToSelect()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopIdiomRecognize.cpp2285 Value *&BitMask, Value *&BitPos, in detectShiftUntilBitTestIdiom() argument
2321 m_Value(BitMask), in detectShiftUntilBitTestIdiom()
2328 m_CombineAnd(m_Value(BitMask), m_Power2()))) && in detectShiftUntilBitTestIdiom()
2329 (BitPos = ConstantExpr::getExactLogBase2(cast<Constant>(BitMask))); in detectShiftUntilBitTestIdiom()
2335 (BitMask = ConstantInt::get(CurrX->getType(), Mask)) && in detectShiftUntilBitTestIdiom()
2440 Value *X, *BitMask, *BitPos, *XCurr; in recognizeShiftUntilBitTest() local
2442 if (!detectShiftUntilBitTestIdiom(CurLoop, X, BitMask, BitPos, XCurr, in recognizeShiftUntilBitTest()
2492 Value *LowBitMask = Builder.CreateAdd(BitMask, Constant::getAllOnesValue(Ty), in recognizeShiftUntilBitTest()
2495 Builder.CreateOr(LowBitMask, BitMask, BitPos->getName() + ".mask"); in recognizeShiftUntilBitTest()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineOperand.cpp557 unsigned BitMask = Flags.second; in printTargetFlags() local
561 if ((BitMask & Mask.first) == Mask.first) { in printTargetFlags()
567 BitMask &= ~(Mask.first); in printTargetFlags()
570 if (BitMask) { in printTargetFlags()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DVOP3PInstructions.td256 class Extract<int FromBitIndex, int BitMask, bit U>: PatFrag<
258 …!if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last elem…
261 !if (U, (and node:$src, (i32 BitMask)),
262 … !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src),
264 !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)),
265 … !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src),
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DModuleSummaryIndexYAML.h35 io.mapOptional("BitMask", res.BitMask);
H A DModuleSummaryIndex.h992 uint8_t BitMask = 0;
/llvm-project-15.0.7/llvm/lib/LTO/
H A DLTO.cpp269 AddUint64(S.TTRes.BitMask); in computeLTOCacheKey()

12