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Searched refs:BaseOps (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInsertHardClauses.cpp179 SmallVector<const MachineOperand *, 4> BaseOps; member
216 SmallVector<const MachineOperand *, 4> BaseOps; in runOnMachineFunction() local
218 if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2, in runOnMachineFunction()
235 !SII->shouldClusterMemOps(CI.BaseOps, BaseOps, 2, 2)))) { in runOnMachineFunction()
251 CI.BaseOps = std::move(BaseOps); in runOnMachineFunction()
256 CI = ClauseInfo{Type, &MI, &MI, 1, 0, std::move(BaseOps)}; in runOnMachineFunction()
H A DSIInstrInfo.cpp319 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
355 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
375 BaseOps.push_back(RSrc); in getMemOperandsWithOffsetWidth()
378 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
386 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
402 BaseOps.push_back(&LdSt.getOperand(SRsrcIdx)); in getMemOperandsWithOffsetWidth()
407 BaseOps.push_back(&LdSt.getOperand(I)); in getMemOperandsWithOffsetWidth()
409 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth()
422 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
435 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
[all …]
H A DSIInstrInfo.h197 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcluster_stores.ll14 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
15 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
16 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
17 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
18 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
19 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
150 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
151 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
152 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
153 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineScheduler.cpp1490 SmallVector<const MachineOperand *, 4> BaseOps; member
1494 MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps, in MemOpInfo()
1496 : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset), in MemOpInfo()
1521 if (std::lexicographical_compare(BaseOps.begin(), BaseOps.end(), in operator <()
1522 RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <()
1525 if (std::lexicographical_compare(RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <()
1526 BaseOps.begin(), BaseOps.end(), Compare)) in operator <()
1626 if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength, in clusterNeighboringMemOps()
1688 SmallVector<const MachineOperand *, 4> BaseOps; in collectMemOpRecords() local
1692 if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, in collectMemOpRecords()
[all …]
H A DTargetInstrInfo.cpp1073 SmallVector<const MachineOperand *, 4> BaseOps; in getMemOperandWithOffset() local
1075 if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, in getMemOperandWithOffset()
1077 BaseOps.size() != 1) in getMemOperandWithOffset()
1079 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h72 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
H A DLanaiInstrInfo.cpp795 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
814 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h209 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
H A DHexagonInstrInfo.cpp3034 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3041 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h142 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
H A DAArch64InstrInfo.cpp2545 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2555 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h343 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
H A DX86InstrInfo.cpp3794 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3833 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h641 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
H A DPPCInstrInfo.cpp2765 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2772 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1349 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3270 SmallVector<SDValue, 1> BaseOps(1, Cond); in visitSelect() local
3361 BaseOps.clear(); in visitSelect()
3367 BaseOps.clear(); in visitSelect()
3383 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()