| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 134 for (const auto &Bank : Banks) in emitHeader() local
217 for (const auto &Bank : Banks) { in emitBaseClassImplementation() local
221 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation()
241 for (const auto &Bank : Banks) { in emitBaseClassImplementation() local
243 (TargetName + "::" + Bank.getEnumeratorName()).str(); in emitBaseClassImplementation()
247 << QualifiedBankID << ", /* Name */ \"" << Bank.getName() in emitBaseClassImplementation()
258 for (const auto &Bank : Banks) in emitBaseClassImplementation() local
283 RegisterBank Bank(*V); in run() local
292 Bank.addRegisterClass(RC); in run()
297 Banks.push_back(Bank); in run()
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| H A D | RegisterInfoEmitter.cpp | 67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
74 CodeGenRegBank &Bank);
78 CodeGenRegBank &Bank);
103 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums() argument
104 const auto &Registers = Bank.getRegisters(); in runEnums()
135 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
189 unsigned NumSets = Bank.getNumRegPressureSets(); in runEnums()
191 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); in runEnums()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 371 const RegisterBank *Bank = in setTypesAccordingToPhysicalRegister() local
374 if (Bank == &Mips::FPRBRegBank) in setTypesAccordingToPhysicalRegister()
376 else if (Bank == &Mips::GPRBRegBank) in setTypesAccordingToPhysicalRegister()
549 const RegisterBankInfo::ValueMapping *Bank = getFprbMapping(Op0Size); in getInstrMapping() local
551 {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank}); in getInstrMapping()
558 const RegisterBankInfo::ValueMapping *Bank = in getInstrMapping() local
561 {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank}); in getInstrMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 214 unsigned BankID = Bank.getID(); in isVectorRegisterBank()
649 MRI->setRegBank(LoLHS, *Bank); in split64BitValueForMapping()
650 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
689 if (Bank == &AMDGPU::SGPRRegBank) in buildReadFirstLane()
695 if (Bank != &AMDGPU::VGPRRegBank) { in buildReadFirstLane()
1013 if (Bank == &AMDGPU::SGPRRegBank) in constrainOpWithReadfirstlane()
2015 MRI.setRegBank(Copy, Bank); in constrainRegToBank()
2019 MRI.setRegBank(Reg, Bank); in constrainRegToBank()
3515 return Bank ? Bank->getID() : Default; in getRegBankID()
3625 if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) { in getInstrMapping()
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| H A D | SIRegisterInfo.h | 320 getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
323 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { in getRegClassForTypeOnBank() argument
324 return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank); in getRegClassForTypeOnBank()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 41 unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, int Bank);
169 int Bank) { in selectIndexedProgMemLoad() argument
176 assert((Bank == 0 || Subtarget->hasELPM()) && in selectIndexedProgMemLoad()
185 Opcode = Bank > 0 ? AVR::ELPMBRdZPi : AVR::LPMRdZPi; in selectIndexedProgMemLoad()
189 Opcode = Bank > 0 ? AVR::ELPMWRdZPi : AVR::LPMWRdZPi; in selectIndexedProgMemLoad()
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| H A D | AVRExpandPseudoInsts.cpp | 830 Register Bank = MI.getOperand(2).getReg(); in expandLPMWELPMW() local
832 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank); in expandLPMWELPMW()
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| /llvm-project-15.0.7/llvm/docs/GlobalISel/ |
| H A D | RegBankSelect.rst | 32 * **Cross-Bank Copies**: ``copyCost`` --- the cost of a ``COPY`` from one bank
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| H A D | Pipeline.rst | 37 :doc:`Register Bank Selector <RegBankSelect>`
64 Register Bank Selector
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| H A D | GMIR.rst | 84 Register Bank
87 A Register Bank is a set of register classes defined by the target. This
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 64 const RegisterBank *Bank; member
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1389 MatchInfo.Bank = getRegBank(Imm2); in matchPtrAddImmedChain()
1399 setRegBank(NewOffset.getReg(0), MatchInfo.Bank); in applyPtrAddImmedChain()
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