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Searched refs:BW (Results 1 – 25 of 51) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector-popcnt-512.ll185 ; AVX512VPOPCNTDQ-BW: # %bb.0:
197 ; AVX512VPOPCNTDQ-BW-NEXT: retq
261 ; AVX512VPOPCNTDQ-BW: # %bb.0:
270 ; AVX512VPOPCNTDQ-BW-NEXT: retq
493 ; AVX512VPOPCNTDQ-BW: # %bb.0:
499 ; AVX512VPOPCNTDQ-BW-NEXT: retq
563 ; AVX512VPOPCNTDQ-BW: # %bb.0:
570 ; AVX512VPOPCNTDQ-BW-NEXT: retq
631 ; AVX512VPOPCNTDQ-BW: # %bb.0:
637 ; AVX512VPOPCNTDQ-BW-NEXT: retq
[all …]
H A Dvector-popcnt-512-ult-ugt.ll49 ; AVX512VPOPCNTDQ-BW: # %bb.0:
54 ; AVX512VPOPCNTDQ-BW-NEXT: retq
106 ; AVX512VPOPCNTDQ-BW: # %bb.0:
111 ; AVX512VPOPCNTDQ-BW-NEXT: retq
191 ; AVX512VPOPCNTDQ-BW: # %bb.0:
202 ; AVX512VPOPCNTDQ-BW-NEXT: retq
293 ; AVX512VPOPCNTDQ-BW-NEXT: retq
384 ; AVX512VPOPCNTDQ-BW-NEXT: retq
475 ; AVX512VPOPCNTDQ-BW-NEXT: retq
566 ; AVX512VPOPCNTDQ-BW-NEXT: retq
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp161 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
162 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
174 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
185 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
200 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
300 while (I*BW < Ws) { in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
H A DHexagonConstPropagation.cpp1590 (void)BW; in evaluateZEXTi()
1630 if (BW <= 64 && Bits != 0) { in evaluateSEXTi()
1655 if (Bits < BW) in evaluateSEXTi()
1767 assert(Bits+Offset <= BW); in evaluateEXTRACTi()
1770 Result = APInt(BW, 0); in evaluateEXTRACTi()
1773 if (BW <= 64) { in evaluateEXTRACTi()
1784 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits); in evaluateEXTRACTi()
1786 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits); in evaluateEXTRACTi()
2157 if (Offset >= BW) { in evaluate()
2162 if (Offset+Bits > BW) { in evaluate()
[all …]
H A DBitTracker.cpp350 uint16_t BW = getRegBitWidth(RR); in getCell() local
355 return RegisterCell::self(0, BW); in getCell()
362 return RegisterCell::self(0, BW); in getCell()
372 return RegisterCell::top(BW); in getCell()
424 uint16_t BW = A.getBitWidth(); in eIMM() local
425 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
426 RegisterCell Res(BW); in eIMM()
427 for (uint16_t i = 0; i < BW; ++i) in eIMM()
H A DHexagonExpandCondsets.cpp236 bool isIntReg(RegisterRef RR, unsigned &BW);
1093 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() argument
1098 BW = 32; in isIntReg()
1102 BW = (RR.Sub != 0) ? 32 : 64; in isIntReg()
H A DHexagonBitSimplify.cpp1363 unsigned BN, BW; in processBlock() local
1364 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in processBlock()
1368 if (!usedBitsEqual(RD, RS) && !HBS::isEqual(DC, 0, SC, BN, BW)) in processBlock()
2182 unsigned BN, BW; in genExtractLow() local
2183 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in genExtractLow()
2185 if (BW < W || !HBS::isEqual(RC, 0, SC, BN, W)) in genExtractLow()
/llvm-project-15.0.7/llvm/test/Transforms/PGOProfile/
H A Dmultiple_hash_profile.ll30 ; CHECK-SAME: !prof ![[BW:[0-9]+]]
31 ; CHECK: ![[BW]] = !{!"branch_weights", i32 12, i32 6}
33 ; CHECKOLDHASH-SAME: !prof ![[BW:[0-9]+]]
34 ; CHECKOLDHASH: ![[BW]] = !{!"branch_weights", i32 6, i32 12}
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp453 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in generateCondForPow() local
455 if (BW == 8) in generateCondForPow()
457 else if (BW == 16) in generateCondForPow()
459 else if (BW == 32) in generateCondForPow()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dnegated-bitmask.ll4 ; PR53610 - sub(0,and(lshr(X,C1),1)) --> ashr(shl(X,(BW-1)-C1),BW-1)
5 ; PR53610 - sub(C2,and(lshr(X,C1),1)) --> add(ashr(shl(X,(BW-1)-C1),BW-1),C2)
H A Dfold-vector-select.ll17 <4 x i32> *%BW, <4 x i32> *%BX, <4 x i32> *%BY, <4 x i32> *%BZ,
133 store <4 x i32> %bw, <4 x i32>* %BW
/llvm-project-15.0.7/llvm/lib/IR/
H A DConstantRange.cpp741 auto BW = getBitWidth(); in castOp() local
742 APInt Min = APInt::getMinValue(BW); in castOp()
743 APInt Max = APInt::getMaxValue(BW); in castOp()
744 if (ResultBitWidth > BW) { in castOp()
752 auto BW = getBitWidth(); in castOp() local
753 APInt SMin = APInt::getSignedMinValue(BW); in castOp()
754 APInt SMax = APInt::getSignedMaxValue(BW); in castOp()
755 if (ResultBitWidth > BW) { in castOp()
1450 unsigned BW = getBitWidth(); in shl() local
1451 if (RHS->uge(BW)) in shl()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DBitVector.h802 BitWord BW = Bits[i]; in applyMask() local
807 if (AddBits) BW |= BitWord(M) << b; in applyMask()
808 else BW &= ~(BitWord(M) << b); in applyMask()
810 Bits[i] = BW; in applyMask()
/llvm-project-15.0.7/clang/test/Lexer/
H A Dbitint-constants.c108 0BW; // expected-error {{invalid digit 'B' in octal constant}} in InvalidSuffix()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp987 unsigned BW = VT.getScalarSizeInBits(); in ExpandSEXTINREG() local
989 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
1365 unsigned BW = VT.getScalarSizeInBits(); in ExpandUINT_TO_FLOAT() local
1366 assert((BW == 64 || BW == 32) && in ExpandUINT_TO_FLOAT()
1369 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT); in ExpandUINT_TO_FLOAT()
1374 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF; in ExpandUINT_TO_FLOAT()
1379 DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0)); in ExpandUINT_TO_FLOAT()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp205 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
206 auto Input = ConstantRange::getFull(BW); in walkBackwards()
H A DConstantHoisting.cpp538 unsigned BW = V1.getBitWidth() > V2.getBitWidth() ? in calculateOffsetDiff() local
547 return APInt(BW, Diff, true); in calculateOffsetDiff()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp257 unsigned BW = X->getType()->getScalarSizeInBits(); in visitImpl() local
258 Constant *BWMinusOne = ConstantInt::get(X->getType(), BW - 1); in visitImpl()
/llvm-project-15.0.7/clang/include/clang/AST/
H A DDeclObjC.h1934 QualType T, TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, in ObjCIvarDecl() argument
1936 : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, in ObjCIvarDecl()
1945 AccessControl ac, Expr *BW = nullptr,
2003 QualType T, Expr *BW) in ObjCAtDefsFieldDecl() argument
2006 BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit) {} in ObjCAtDefsFieldDecl()
2014 QualType T, Expr *BW);
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp1261 unsigned BW = OffsetRange.getBitWidth(); in aliasGEP() local
1263 ConstantRange(APInt(BW, 0), APInt(BW, V1Size.getValue()))); in aliasGEP()
1265 ConstantRange(APInt(BW, 0), APInt(BW, V2Size.getValue())); in aliasGEP()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp353 unsigned BW = DL.getIndexTypeSizeInBits(GEP->getType()); in GEPToVectorIndex() local
355 APInt ConstOffset(BW, 0); in GEPToVectorIndex()
357 !GEP->collectOffset(DL, BW, VarOffsets, ConstOffset)) in GEPToVectorIndex()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td420 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
423 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
427 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
428 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
/llvm-project-15.0.7/clang/lib/AST/
H A DDeclObjC.cpp1808 AccessControl ac, Expr *BW, in Create() argument
1836 return new (C, DC) ObjCIvarDecl(DC, StartLoc, IdLoc, Id, T, TInfo, ac, BW, in Create()
1884 IdentifierInfo *Id, QualType T, Expr *BW) { in Create() argument
1885 return new (C, DC) ObjCAtDefsFieldDecl(DC, StartLoc, IdLoc, Id, T, BW); in Create()

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