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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-bswap.mir29 ; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s16) = G_BSWAP [[TRUNC]]
67 ; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s16) = G_BSWAP [[TRUNC]]
100 ; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
121 ; GFX7-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
122 ; GFX7-NEXT: $vgpr0 = COPY [[BSWAP]](s32)
127 ; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
128 ; GFX8-NEXT: $vgpr0 = COPY [[BSWAP]](s32)
175 ; GFX8-NEXT: $vgpr0 = COPY [[BSWAP]](<2 x s16>)
354 ; GFX7-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
363 ; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
[all …]
H A Dregbankselect-bswap.mir17 ; CHECK-NEXT: [[BSWAP:%[0-9]+]]:vgpr(s32) = G_BSWAP [[COPY1]]
33 ; CHECK-NEXT: [[BSWAP:%[0-9]+]]:vgpr(s32) = G_BSWAP [[COPY]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbswap-inseltpoison.ll49 ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 …
50 ; CHECK-NEXT: call void @use(<4 x i8> [[BSWAP]])
51 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
64 ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <16 x i8> [[X:%.*]], <16 x i8> poison, <16 x i32> <i…
65 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i8> [[BSWAP]] to i128
77 ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 …
78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
H A Dbswap.ll270 ; CHECK-NEXT: [[BSWAP:%.*]] = call i32 @llvm.bswap.i32(i32 [[X:%.*]])
271 ; CHECK-NEXT: ret i32 [[BSWAP]]
292 ; CHECK-NEXT: [[BSWAP:%.*]] = call i32 @llvm.bswap.i32(i32 [[X]])
294 ; CHECK-NEXT: ret i32 [[BSWAP]]
315 ; CHECK-NEXT: ret i32 [[BSWAP]]
336 ; CHECK-NEXT: [[BSWAP:%.*]] = call i32 @llvm.bswap.i32(i32 [[X]])
338 ; CHECK-NEXT: ret i32 [[BSWAP]]
695 ; CHECK-NEXT: call void @use(<4 x i8> [[BSWAP]])
696 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
710 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i8> [[BSWAP]] to i128
[all …]
H A Dbswap-fold.ll269 ; Fold: OP( BSWAP(x), BSWAP(y) ) -> BSWAP( OP(x, y) )
270 ; Fold: OP( BSWAP(x), CONSTANT ) -> BSWAP( OP(x, BSWAP(CONSTANT) ) )
H A Dor-concat.ll11 ; BSWAP
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dload-combine.ll44 ; BSWAP: # %bb.0:
48 ; BSWAP-NEXT: retl
178 ; BSWAP: # %bb.0:
182 ; BSWAP-NEXT: retl
280 ; BSWAP: # %bb.0:
286 ; BSWAP-NEXT: retl
658 ; BSWAP-NEXT: retl
705 ; BSWAP-NEXT: retl
753 ; BSWAP-NEXT: retl
836 ; BSWAP-NEXT: retl
[all …]
H A Dbswap-rotate.ll5 ; Combine BSWAP (lowered to rolw 8) with a second rotate.
H A Dbswap-vector.ll262 ; Double BSWAP -> Identity
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-bswap.mir15 ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
17 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
121 ; CHECK: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[DEF]]
124 ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
145 ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[DEF]]
147 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
H A Dprelegalizer-combiner-load-or-pattern.mir26 ; -> Big endian: Load from x[0] + BSWAP
91 ; -> Little endian: Load from x[0] + BSWAP
150 ; -> Big endian: Load from x[0] + BSWAP
217 ; -> Big endian: Load from x[0] + BSWAP
257 ; -> Little endian: Load from x[0] + BSWAP
299 ; -> Big endian: Load from x[0] + BSWAP
355 ; -> Little endian: Load from x[0] + BSWAP
413 ; -> Big endian: Load from x[1] + BSWAP
474 ; -> Little endian: Load from x[1] + BSWAP
537 ; -> Big endian: Load from x[-3] + BSWAP
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dbswap.mir20 ; MIPS32R2: [[BSWAP:%[0-9]+]]:gprb(s32) = G_BSWAP [[COPY]]
21 ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dbswap.mir38 ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
39 ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
87 ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
89 ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
H A Dbitreverse.mir59 ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
62 ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
64 ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
165 ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
168 ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
170 ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td838 class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern>
854 def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
855 def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
856 def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>;
859 def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
860 def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
861 def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>;
H A DBPFISelLowering.cpp123 setOperationAction(ISD::BSWAP, MVT::i32, Promote); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2903 { ISD::BSWAP, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2904 { ISD::BSWAP, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2905 { ISD::BSWAP, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2946 { ISD::BSWAP, MVT::v8i64, 4 }, in getTypeBasedIntrinsicInstrCost()
2947 { ISD::BSWAP, MVT::v16i32, 4 }, in getTypeBasedIntrinsicInstrCost()
2948 { ISD::BSWAP, MVT::v32i16, 4 }, in getTypeBasedIntrinsicInstrCost()
3037 { ISD::BSWAP, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
3038 { ISD::BSWAP, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
3039 { ISD::BSWAP, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3104 { ISD::BSWAP, MVT::v4i64, 4 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h700 BSWAP, enumerator
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp146 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in Mips16TargetLowering()
147 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in Mips16TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp659 ISD::BSWAP, in SystemZTargetLowering()
6408 Op1.getOpcode() == ISD::BSWAP && in combineSTORE()
6578 if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) { in combineEXTRACT_VECTOR_ELT()
6584 Op = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Op); in combineEXTRACT_VECTOR_ELT()
6843 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() || in combineBSWAP()
6845 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() || in combineBSWAP()
6858 Vec = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Vec); in combineBSWAP()
6860 Elt = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Elt); in combineBSWAP()
6874 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() || in combineBSWAP()
6876 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) { in combineBSWAP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp982 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); in LowerShifts()
987 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); in LowerShifts()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp342 case ISD::BSWAP: in LegalizeOp()
728 case ISD::BSWAP: in Expand()
H A DSelectionDAGDumper.cpp431 case ISD::BSWAP: return "bswap"; in getOperationName()
/llvm-project-15.0.7/llvm/docs/
H A DExtendingLLVM.rst121 well. For a good example, see ``ISD::BSWAP``, which promotes its operand to
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp457 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); in PPCTargetLowering()
459 setOperationAction(ISD::BSWAP, MVT::i64 , Custom); in PPCTargetLowering()
461 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); in PPCTargetLowering()
858 setOperationAction(ISD::BSWAP, VT, Expand); in PPCTargetLowering()
1231 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal); in PPCTargetLowering()
1232 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal); in PPCTargetLowering()
10713 Op = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Op); in LowerBSWAP()
11216 case ISD::BSWAP: in LowerOperation()
15600 case ISD::BSWAP: { in PerformDAGCombine()
15654 Lo = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Lo); in PerformDAGCombine()
[all …]

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