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/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Dpr48051.ll25 ; CHECK-NEXT: [[B16:%.*]] = urem i64 [[B4]], [[B9]]
26 ; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], [[B16]]
52 %B16 = urem i64 %B4, %B9
53 %i.next = add i64 %i, %B16
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULibFunc.h255 B16 = 2, enumerator
264 U16 = UINT | B16,
268 I16 = INT | B16,
271 F16 = FLOAT | B16,
H A DSIRegisterInfo.td925 let ParserMatchClass = RegImmMatcher<MatchName#"B16">;
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Ddag-combine-ossfuzz-crash.ll38 %B16 = urem i66 %B22, %L6
39 %G47 = getelementptr i66, i66* %G8, i66 %B16
/llvm-project-15.0.7/llvm/test/Transforms/ADCE/
H A D2016-09-06.ll31 br i1 %I15, label %B16, label %B20
33 B16:
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dbin_power.ll92 ; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
93 ; CHECK-NEXT: [[B27:[^ ]+]] = mul i32 [[B11]], [[B16]]
135 ; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
136 ; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B16]], -1
232 ; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/AArch64/
H A Dsubreg-fragment-overflow.mir5 # CHECK: DW_OP_piece 0x8, DW_OP_regx B16, DW_OP_piece 0x8
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A DsplitMove_undefReg_mverifier.ll44 %B16 = fsub double 0xDACBFCEAC1C99968, 0xDACBFCEAC1C99968
127 %B61 = frem double 0x5A7FED9E637D2C1C, %B16
195 %Cmp103 = fcmp ord double %B16, 0xDACBFCEAC1C99968
321 %Cmp181 = fcmp ugt double %B61, %B16
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h146 case AArch64::D16: return AArch64::B16; in getBRegFromDReg()
186 case AArch64::B16: return AArch64::D16; in getDRegFromBReg()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmax.ll232 ; SI-DAG: s_and_b32 [[B16:s[0-9]+]], [[B]], 0xffff
233 ; SI: s_max_u32 [[MAX:s[0-9]+]], [[A16]], [[B16]]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfold-vector-shuffle-crash.ll48 %B16 = add <2 x i64> zeroinitializer, <i64 -1, i64 -1>
167 %Cmp101 = icmp ne <2 x i64> %B16, zeroinitializer
181 %I113 = insertelement <2 x i64> %B16, i64 %E95, i32 0
H A Dcombine-srem.ll418 %B16 = srem i32 %L6, %B14
420 %B6 = and i32 %B16, %B10
H A Dcrash.ll328 %B16 = frem <8 x double> zeroinitializer, %Shuff
340 %B55 = fmul <8 x double> %B16, undef
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td276 def B16 : AArch64Reg<16, "b16">, DwarfRegNum<[80]>;
310 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
345 def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>;
380 def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
415 def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp250 {codeview::RegisterId::ARM64_B16, AArch64::B16}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1031 CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_2, M2, B16) in Select()
1091 CASE_VMSLT_OPCODES(LMUL_2, M2, B16) in Select()
H A DRISCVInstrInfoVPseudos.td312 def : MTypeInfo<vbool4_t, V_M2, "B16">;
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshift.ll1778 %B16 = add i32 %B2, %i3
1784 %C7 = icmp sle i32 %i3, %B16
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-add-saddo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A16]], i8 [[B16]])
H A Darith-add-uaddo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A16]], i8 [[B16]])
H A Darith-mul-umulo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A16]], i8 [[B16]])
H A Darith-mul-smulo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A16]], i8 [[B16]])
H A Darith-sub-ssubo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A16]], i8 [[B16]])
H A Darith-sub-usubo.ll332 ; CHECK-NEXT: [[B16:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
364 ; CHECK-NEXT: [[C16:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A16]], i16 [[B16…
691 ; CHECK-NEXT: [[B16:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
755 ; CHECK-NEXT: [[C16:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A16]], i8 [[B16]])
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dfunnel_shift.ll114 ; CHECK-NEXT: [[I16:%.*]] = call i16 @llvm.fshl.i16(i16 [[A16:%.*]], i16 [[B16:%.*]], i16 [[C16]…