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Searched refs:AndReg (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp392 Register AndReg = MRI->createVirtualRegister(BoolRC); in emitIfBreak() local
393 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
399 .addReg(AndReg) in emitIfBreak()
402 LIS->createAndComputeVirtRegInterval(AndReg); in emitIfBreak()
H A DSIInstrInfo.cpp5539 Register AndReg = MRI.createVirtualRegister(BoolXExecRC); in emitLoadSRsrcFromVGPRLoop() local
5540 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg) in emitLoadSRsrcFromVGPRLoop()
5543 CondReg = AndReg; in emitLoadSRsrcFromVGPRLoop()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp498 Register AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in LowerFPToInt() local
502 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
503 CmpReg = AndReg; in LowerFPToInt()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp3024 Register AndReg = MI.getOperand(1).getReg(); in matchXorOfAndWithSameReg() local
3032 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) { in matchXorOfAndWithSameReg()
3033 std::swap(AndReg, SharedReg); in matchXorOfAndWithSameReg()
3034 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) in matchXorOfAndWithSameReg()
3039 if (!MRI.hasOneNonDBGUse(AndReg)) in matchXorOfAndWithSameReg()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp2264 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect() local
2266 Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, AndReg); in X86FastEmitSSESelect()