Searched refs:AndLHS (Results 1 – 7 of 7) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 586 Value *AndLHS, *AndRHS; in parseRangeChecks() local
587 if (match(CheckCond, m_And(m_Value(AndLHS), m_Value(AndRHS)))) in parseRangeChecks()
588 return parseRangeChecks(AndLHS, Checks) && in parseRangeChecks()
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1473 SDValue AndLHS = Op0; in LowerAndToBTST() local
1475 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { in LowerAndToBTST()
1476 LHS = AndLHS.getOperand(0); in LowerAndToBTST()
1477 RHS = AndLHS.getOperand(1); in LowerAndToBTST()
1482 LHS = AndLHS; in LowerAndToBTST()
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 3446 SDValue AndLHS = LHS->getOperand(0); in tryBFE() local
3450 if (isa<ConstantSDNode>(AndLHS)) { in tryBFE()
3451 std::swap(AndLHS, AndRHS); in tryBFE()
3486 Val = AndLHS; in tryBFE()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2287 const Value *AndLHS = AI->getOperand(0); in emitCompareAndBranch() local
2290 if (const auto *C = dyn_cast<ConstantInt>(AndLHS)) in emitCompareAndBranch()
2292 std::swap(AndLHS, AndRHS); in emitCompareAndBranch()
2297 LHS = AndLHS; in emitCompareAndBranch()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4659 Register AndLHS = MI.getOperand(1).getReg(); in matchNarrowBinopFeedingAnd() local
4665 if (!WideTy.isScalar() || !MRI.hasOneNonDBGUse(AndLHS)) in matchNarrowBinopFeedingAnd()
4674 MachineInstr *LHSInst = getDefIgnoringCopies(AndLHS, MRI); in matchNarrowBinopFeedingAnd()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 24143 SDValue AndLHS = N0->getOperand(0); in SimplifySelectCC() local
24151 DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS), in SimplifySelectCC()
24152 getShiftAmountTy(AndLHS.getValueType())); in SimplifySelectCC()
24153 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); in SimplifySelectCC()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24033 SDValue AndLHS = Op0; in LowerAndToBT() local
24035 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { in LowerAndToBT()
24036 Src = AndLHS.getOperand(0); in LowerAndToBT()
24037 BitNo = AndLHS.getOperand(1); in LowerAndToBT()
24044 Src = AndLHS; in LowerAndToBT()
|