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Searched refs:AfterLegalizeVectorOps (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DDAGCombine.h18 AfterLegalizeVectorOps, enumerator
H A DTargetLowering.h3821 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp811 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC()
H A DSIISelLowering.cpp5761 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp868 CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel); in CodeGenAndEmitDAG()
H A DDAGCombiner.cpp1573 LegalOperations = Level >= AfterLegalizeVectorOps; in Run()
4005 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) { in visitMUL()
13311 if (Level == AfterLegalizeVectorOps && VT.isVector() && in visitTRUNCATE()
20077 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) in reduceBuildVecExtToExtBuildVec()
21229 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) { in visitCONCAT_VECTORS()
22611 Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()
22647 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT) && in visitVECTOR_SHUFFLE()
22774 N1.isUndef() && Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()