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Searched refs:AddrBaseReg (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InsertPrefetch.cpp83 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
218 static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
226 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
H A DX86OptimizeLEAs.cpp194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
460 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
466 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
559 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
H A DX86FixupLEAs.cpp462 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage()
514 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU()
561 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
664 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
701 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
753 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
H A DX86AsmPrinter.cpp289 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
326 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
385 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
413 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
H A DX86CallFrameOptimization.cpp427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
H A DX86SpeculativeLoadHardening.cpp1337 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1411 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1813 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
H A DX86InstrInfo.h122 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
H A DX86AvoidStoreForwardingBlocks.cpp301 return MI->getOperand(AddrOffset + X86::AddrBaseReg); in getBaseOperand()
H A DX86LoadValueInjectionLoadHardening.cpp787 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in instrUsesRegToAccessMemory()
H A DX86InstrInfo.cpp455 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && in isFrameOperand()
462 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); in isFrameOperand()
868 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
873 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
893 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
895 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
3707 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp()
3805 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandsWithOffsetWidth()
7318 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || in areLoadsFromSameBasePtr()
H A DX86MCInstLower.cpp389 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
413 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in SimplifyShortMoveForm()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp328 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
815 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
862 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
878 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
895 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
922 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1174 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in emitREXPrefix()
1183 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in emitREXPrefix()
1198 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in emitREXPrefix()
H A DX86MCTargetDesc.cpp77 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
87 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
97 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
649 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()
675 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset()
H A DX86IntelInstPrinter.cpp383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
395 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
H A DX86ATTInstPrinter.cpp426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
447 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
H A DX86AsmBackend.cpp265 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg; in isRIPRelative()
341 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg; in determinePaddingPrefix()
H A DX86BaseInfo.h32 AddrBaseReg = 0, enumerator
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCSymbolizer.cpp62 const MCOperand &Base = Inst.getOperand(MemOp + X86::AddrBaseReg); in tryAddingSymbolicOperand()
H A DX86MCPlusBuilder.cpp418 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) in match()
505 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) in match()
601 (CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != in match()
603 CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != X86::RIP)) in match()
690 const MCOperand &Base = Inst.getOperand(MemOpOffset + X86::AddrBaseReg); in evaluateX86MemoryOperand()