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Searched refs:AMDGPUTargetLowering (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp58 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
729 SDValue AMDGPUTargetLowering::getNegatedExpression( in getNegatedExpression()
753 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const { in isFAbsFree()
761 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const { in isFNegFree()
1038 SDValue AMDGPUTargetLowering::LowerReturn( in LowerReturn()
1142 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, in LowerOperation()
1683 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op, in LowerUDIVREM64()
1899 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, in LowerUDIVREM()
1954 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op, in LowerSDIVREM()
3186 SDValue AMDGPUTargetLowering::performTruncateCombine( in performTruncateCombine()
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H A DR600TargetTransformInfo.h26 class AMDGPUTargetLowering; variable
35 const AMDGPUTargetLowering *TLI;
42 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
H A DAMDGPUCallLowering.h21 class AMDGPUTargetLowering; variable
41 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
H A DR600ISelLowering.h24 class R600TargetLowering final : public AMDGPUTargetLowering {
H A DAMDGPUISelLowering.h27 class AMDGPUTargetLowering : public TargetLowering {
150 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
H A DR600ISelLowering.cpp31 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) { in R600TargetLowering()
236 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
398 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
582 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
671 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1820 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
1924 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
H A DAMDGPUISelDAGToDAG.cpp1520 N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode(); in findMemSDNode()
1526 dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V))) in findMemSDNode()
2980 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG()
2981 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); in PostprocessISelDAG()
H A DSIISelLowering.h31 class SITargetLowering final : public AMDGPUTargetLowering {
H A DAMDGPULegalizerInfo.cpp1861 AMDGPUTargetLowering::ImplicitParameter Param = in getSegmentAperture()
1862 AS == AMDGPUAS::LOCAL_ADDRESS ? AMDGPUTargetLowering::SHARED_BASE in getSegmentAperture()
1863 : AMDGPUTargetLowering::PRIVATE_BASE; in getSegmentAperture()
4169 B.getMF(), AMDGPUTargetLowering::FIRST_IMPLICIT); in getImplicitArgPtr()
5305 AMDGPUTargetLowering::ImplicitParameter Param = in legalizeTrapHsaQueuePtr()
5306 AMDGPUTargetLowering::QUEUE_PTR; in legalizeTrapHsaQueuePtr()
H A DAMDGPUCallLowering.cpp248 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) in AMDGPUCallLowering()
H A DSIISelLowering.cpp78 : AMDGPUTargetLowering(TM, STI), in SITargetLowering()
2608 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, in LowerReturn()
3417 return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerDYNAMIC_STACKALLOC()
4422 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
4647 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
6076 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
9996 return AMDGPUTargetLowering::performRcpCombine(N, DCI); in performRcpCombine()
11548 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
12705 return AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(Op, DAG, in isKnownNeverNaNForTargetNode()
12811 return AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(RMW); in shouldExpandAtomicRMWInIR()