39 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {  in getEquivalentMemType()
48 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {  in numBitsUnsigned()
52 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {  in numBitsSigned()
58 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,  in AMDGPUTargetLowering()  function in AMDGPUTargetLowering
480 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {  in mayIgnoreSignedZero()
574 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,  in allUsesHaveSourceMods()
598 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,  in getTypeForExtReturn()
609 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {  in getVectorIdxTy()
613 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {  in isSelectSupported()
619 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
627 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {  in ShouldShrinkFPConstant()
632 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,  in shouldReduceLoadWidth()
671 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,  in isLoadBitCastBeneficial()
696 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
700 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
704 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {  in isSDNodeAlwaysUniform()
729 SDValue AMDGPUTargetLowering::getNegatedExpression(  in getNegatedExpression()
753 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {  in isFAbsFree()
761 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
768 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,  in storeOfVectorConstantIsCheap()
774 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {  in aggressivelyPreferBuildVectorSources()
786 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {  in isTruncateFree()
795 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {  in isTruncateFree()
807 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {  in isZExtFree()
817 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {  in isZExtFree()
829 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
833 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
922 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(  in analyzeFormalArgumentsCompute()
1038 SDValue AMDGPUTargetLowering::LowerReturn(  in LowerReturn()
1055 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
1060 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,  in CCAssignFnForReturn()
1065 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
1099 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,  in lowerUnhandledCall()
1126 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
1131 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
1142 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
1184 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
1201 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,  in LowerGlobalAddress()
1245 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
1265 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
1296 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,  in combineFMinMaxLegacy()
1370 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {  in split64BitValue()
1384 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {  in getLoHalf64()
1392 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {  in getHiHalf64()
1404 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {  in getSplitDestVTs()
1419 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,  in splitVector()
1434 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,  in SplitVectorLoad()
1494 SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,  in WidenOrSplitVectorLoad()
1528 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,  in SplitVectorStore()
1572 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,  in LowerDIVREM24()
1683 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,  in LowerUDIVREM64()
1899 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,  in LowerUDIVREM()
1954 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,  in LowerSDIVREM()
2015 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {  in LowerFREM()
2029 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {  in LowerFCEIL()
2069 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {  in LowerFTRUNC()
2115 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFRINT()
2142 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFNEARBYINT()
2154 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND()
2183 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {  in LowerFFLOOR()
2208 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,  in LowerFLOG()
2221 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {  in lowerFEXP()
2239 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {  in LowerCTLZ_CTTZ()
2291 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP32()
2417 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP64()
2436 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,  in LowerUINT_TO_FP()
2473 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,  in LowerSINT_TO_FP()
2513 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,  in LowerFP_TO_INT64()
2586 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_FP16()
2685 SDValue AMDGPUTargetLowering::LowerFP_TO_INT(SDValue Op,  in LowerFP_TO_INT()
2720 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,  in LowerSIGN_EXTEND_INREG()
2748   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;  in isU24()
2755          AMDGPUTargetLowering::numBitsSigned(Op, DAG) <= 24;  in isI24()
2832 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {  in shouldCombineMemoryType()
2853 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,  in performLoadCombine()
2906 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,  in performStoreCombine()
2963 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,  in performAssertSZExtCombine()
2986 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(  in performIntrinsicWOChainCombine()
3012 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(  in splitBinaryBitConstantOpImpl()
3035 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,  in performShlCombine()
3103 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,  in performSraCombine()
3138 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,  in performSrlCombine()
3186 SDValue AMDGPUTargetLowering::performTruncateCombine(  in performTruncateCombine()
3291 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,  in performMulCombine()
3346 AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,  in performMulLoHiCombine()
3389 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,  in performMulhsCombine()
3422 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,  in performMulhuCombine()
3461 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,  in getFFBX_U32()
3488 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,  in performCtlz_CttzCombine()
3605 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,  in performSelectCombine()
3663 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {  in isConstantCostlierToNegate()
3694 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,  in performFNegCombine()
3904 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,  in performFAbsCombine()
3929 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,  in performRcpCombine()
3941 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
4152 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
4188 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,  in loadStackInputValue()
4204 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,  in storeStackInputValue()
4223 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,  in loadInputValue()
4244 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
4268 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
4420 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,  in getSqrtEstimate()
4438 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
4472 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
4630 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
4671 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(  in computeNumSignBitsForTargetInstr()
4694 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,  in isKnownNeverNaNForTargetNode()
4808 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {  in shouldExpandAtomicRMWInIR()
4821 bool AMDGPUTargetLowering::isConstantUnsignedBitfieldExtractLegal(  in isConstantUnsignedBitfieldExtractLegal()