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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
389 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
395 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
396 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
397 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dr600.extract-lowbits.ll26 ; EG-NEXT: ALU clause starting at 4:
37 ; CM-NEXT: ALU clause starting at 4:
51 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
59 ; EG-NEXT: ALU clause starting at 8:
61 ; EG-NEXT: ALU clause starting at 9:
70 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
78 ; CM-NEXT: ALU clause starting at 8:
80 ; CM-NEXT: ALU clause starting at 9:
159 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
178 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
[all …]
H A Dr600.bitcast.ll9 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
17 ; EG-NEXT: ALU clause starting at 8:
19 ; EG-NEXT: ALU clause starting at 9:
40 ; EG-NEXT: ALU clause starting at 8:
42 ; EG-NEXT: ALU clause starting at 9:
62 ; EG-NEXT: ALU clause starting at 8:
64 ; EG-NEXT: ALU clause starting at 9:
84 ; EG-NEXT: ALU clause starting at 8:
86 ; EG-NEXT: ALU clause starting at 9:
106 ; EG-NEXT: ALU clause starting at 8:
[all …]
H A Dmul_uint24-r600.ll8 ; CM-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
12 ; CM-NEXT: ALU clause starting at 4:
28 ; EG-NEXT: ALU clause starting at 4:
49 ; CM-NEXT: ALU 0, @10, KC0[], KC1[]
58 ; CM-NEXT: ALU clause starting at 10:
60 ; CM-NEXT: ALU clause starting at 11:
72 ; EG-NEXT: ALU 0, @10, KC0[], KC1[]
81 ; EG-NEXT: ALU clause starting at 10:
83 ; EG-NEXT: ALU clause starting at 11:
99 ; CM-NEXT: ALU 0, @10, KC0[], KC1[]
[all …]
H A Dkernel-args.ll46 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
54 ; EG-NEXT: ALU clause starting at 8:
56 ; EG-NEXT: ALU clause starting at 9:
62 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
70 ; CM-NEXT: ALU clause starting at 8:
72 ; CM-NEXT: ALU clause starting at 9:
118 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
135 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
193 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
210 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
[all …]
H A Dstructurize.ll22 ; CHECK: ALU
23 ; === Duplicated diamond_true block (There can be more than one ALU clause):
27 ; CHECK: ALU
34 ; === diamond_true block (There can be more than one ALU clause):
35 ; ALU
43 ; CHECK: ALU
H A Dbfi_int.r600.ll10 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
14 ; R600-NEXT: ALU clause starting at 4:
32 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
36 ; R600-NEXT: ALU clause starting at 4:
53 ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
57 ; R600-NEXT: ALU clause starting at 4:
132 ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
136 ; R600-NEXT: ALU clause starting at 4:
163 ; R600-NEXT: ALU clause starting at 4:
190 ; R600-NEXT: ALU clause starting at 4:
[all …]
H A Dselectcc-icmp-select-float.ll9 ; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
11 ; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
17 ; CHECK-NEXT: ALU clause starting at 8:
19 ; CHECK-NEXT: ALU clause starting at 9:
H A Dsrl.ll50 ; EG-NEXT: ALU clause starting at 8:
52 ; EG-NEXT: ALU clause starting at 9:
109 ; EG-NEXT: ALU clause starting at 8:
111 ; EG-NEXT: ALU clause starting at 9:
177 ; EG-NEXT: ALU clause starting at 10:
179 ; EG-NEXT: ALU clause starting at 11:
237 ; EG-NEXT: ALU clause starting at 8:
239 ; EG-NEXT: ALU clause starting at 9:
323 ; EG-NEXT: ALU clause starting at 14:
401 ; EG-NEXT: ALU clause starting at 4:
[all …]
H A Dr600-legalize-umax-bug.ll8 ; CHECK-NEXT: ALU 4, @6, KC0[CB0:0-32], KC1[]
10 ; CHECK-NEXT: ALU 3, @11, KC0[], KC1[]
14 ; CHECK-NEXT: ALU clause starting at 6:
20 ; CHECK-NEXT: ALU clause starting at 11:
H A Dshl.ll55 ; EG-NEXT: ALU clause starting at 8:
57 ; EG-NEXT: ALU clause starting at 9:
123 ; EG-NEXT: ALU clause starting at 10:
125 ; EG-NEXT: ALU clause starting at 11:
190 ; EG-NEXT: ALU clause starting at 10:
192 ; EG-NEXT: ALU clause starting at 11:
264 ; EG-NEXT: ALU clause starting at 10:
267 ; EG-NEXT: ALU clause starting at 12:
330 ; EG-NEXT: ALU 0, @12, KC0[], KC1[]
499 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
[all …]
H A Dctpop16.ll43 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
51 ; EG-NEXT: ALU clause starting at 8:
53 ; EG-NEXT: ALU clause starting at 9:
118 ; EG-NEXT: ALU clause starting at 8:
121 ; EG-NEXT: ALU clause starting at 10:
204 ; EG-NEXT: ALU clause starting at 12:
207 ; EG-NEXT: ALU clause starting at 14:
209 ; EG-NEXT: ALU clause starting at 15:
281 ; EG-NEXT: ALU 0, @14, KC0[], KC1[]
376 ; EG-NEXT: ALU clause starting at 8:
[all …]
H A Dctlz_zero_undef.ll50 ; EG-NEXT: ALU clause starting at 4:
116 ; EG-NEXT: ALU clause starting at 8:
120 ; EG-NEXT: ALU clause starting at 11:
193 ; EG-NEXT: ALU clause starting at 8:
197 ; EG-NEXT: ALU clause starting at 11:
276 ; EG-NEXT: ALU clause starting at 8:
280 ; EG-NEXT: ALU clause starting at 11:
358 ; EG-NEXT: ALU clause starting at 8:
360 ; EG-NEXT: ALU clause starting at 9:
441 ; EG-NEXT: ALU clause starting at 4:
[all …]
H A Dsra.ll57 ; EG-NEXT: ALU clause starting at 8:
59 ; EG-NEXT: ALU clause starting at 9:
128 ; EG-NEXT: ALU clause starting at 10:
130 ; EG-NEXT: ALU clause starting at 11:
215 ; EG-NEXT: ALU clause starting at 8:
217 ; EG-NEXT: ALU clause starting at 9:
334 ; EG-NEXT: ALU clause starting at 8:
336 ; EG-NEXT: ALU clause starting at 9:
439 ; EG-NEXT: ALU clause starting at 4:
499 ; EG-NEXT: ALU clause starting at 8:
[all …]
H A Dcttz_zero_undef.ll47 ; EG-NEXT: ALU clause starting at 4:
113 ; EG-NEXT: ALU clause starting at 8:
117 ; EG-NEXT: ALU clause starting at 11:
190 ; EG-NEXT: ALU clause starting at 8:
194 ; EG-NEXT: ALU clause starting at 11:
273 ; EG-NEXT: ALU clause starting at 8:
335 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
343 ; EG-NEXT: ALU clause starting at 8:
345 ; EG-NEXT: ALU clause starting at 9:
406 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
[all …]
H A Dmul_int24.ll58 ; EG-NEXT: ALU clause starting at 4:
75 ; CM-NEXT: ALU clause starting at 4:
142 ; EG-NEXT: ALU clause starting at 4:
159 ; CM-NEXT: ALU clause starting at 4:
352 ; EG-NEXT: ALU clause starting at 4:
370 ; CM-NEXT: ALU clause starting at 4:
446 ; EG-NEXT: ALU clause starting at 4:
462 ; CM-NEXT: ALU clause starting at 4:
553 ; EG-NEXT: ALU clause starting at 4:
572 ; CM-NEXT: ALU clause starting at 4:
[all …]
H A Dcttz.ll55 ; EG-NEXT: ALU clause starting at 4:
139 ; EG-NEXT: ALU clause starting at 8:
143 ; EG-NEXT: ALU clause starting at 11:
236 ; EG-NEXT: ALU clause starting at 8:
240 ; EG-NEXT: ALU clause starting at 11:
348 ; EG-NEXT: ALU clause starting at 8:
352 ; EG-NEXT: ALU clause starting at 11:
459 ; EG-NEXT: ALU clause starting at 8:
461 ; EG-NEXT: ALU clause starting at 9:
548 ; EG-NEXT: ALU clause starting at 4:
[all …]
H A Dlds-output-queue.ll4 ; the ALU clause.
8 ; CHECK-NOT: ALU clause
53 ; The bottom scheduler will schedule the two ALU instructions first:
78 ; different ALU clauses.
89 ; CHECK-NOT: ALU clause
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td784 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
793 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
812 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
824 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
834 // Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
856 // Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
981 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
990 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1006 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1046 // One is three cycle ALU the ohter is a two cycle ALU.
[all …]
H A DP10InstrResources.td888 // 2 Cycles ALU operations, 1 input operands
895 // 3 Cycles ALU operations, 0 input operands
909 // 3 Cycles ALU operations, 1 input operands
978 // 3 Cycles ALU operations, 2 input operands
1204 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
1214 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands
1227 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands
1242 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 3 input operands
1249 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 4 input operands
1256 // 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU oper…
[all …]
H A DPPCScheduleP9.td87 // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
88 def ALU : ProcResource<4>;
90 //Even ALU pipelines
91 let Super = ALU;
94 //Odd ALU pipelines
95 let Super = ALU;
189 // ALU Units
190 // An ALU may take either 2 or 3 cycles to complete the operation.
191 // However, the ALU unit is only ever busy for 1 cycle at a time and may
193 def P9_ALU_2C : SchedWriteRes<[ALU]> {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td10 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/
H A DA55-2-skewed-alu.s7 # Cortex-A55 has a secondary skewed ALU in the Ex1 stage for simple
8 # ALU instructions that do not require shifting or saturation
9 # resources. Results from the skewed ALU are available 1 cycle earlier.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcortex-a57-misched-alu.ll5 ; Check the latency for ALU shifted operand variants.
10 ; ALU, basic - 1 cyc I0/I1
15 ; ALU, shift by immed - 2 cyc M
20 ; ALU, shift by register, unconditional - 2 cyc M
25 ; ALU, shift by register, conditional - 2 cyc I0/I1
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg

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