Lines Matching refs:ALU

25 //     - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
33 // Two cycle ALU vector operation that uses an entire superslice.
34 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
86 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
176 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
204 // Three cycle ALU vector operation that uses an entire superslice.
205 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
451 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
460 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
467 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
784 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
793 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
803 // Consecutive Store and ALU instructions. The store is restricted and requires
812 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
824 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
834 // Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
844 // Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
845 // cycles. The Load and ALU operations cannot be done at the same time and so
856 // Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
868 // Load with two ALU operations that depend on each other
981 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
983 // superslice. Latency of DIV plus ALU is 26.
990 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
992 // superslice. Latency of DIV plus ALU is 26.
1006 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1008 // superslice. Latency of DIV plus ALU is 42.
1020 // Cracked, restricted, ALU operations.
1021 // Here the two ALU ops can actually be done in parallel and therefore the
1023 // instructions running together on two pipelines and 6 dispatches. ALU ops are
1032 // Cracked ALU operations.
1033 // Here the two ALU ops can actually be done in parallel and therefore the
1035 // instructions running together on two pipelines and 2 dispatches. ALU ops are
1044 // Cracked ALU operations.
1045 // Two ALU ops can be done in parallel.
1046 // One is three cycle ALU the ohter is a two cycle ALU.
1047 // One of the ALU ops is restricted the other is not so we have a total of
1058 // Cracked ALU operations.
1059 // Here the two ALU ops can actually be done in parallel and therefore the
1062 // ALU ops are 3 cycles each.
1069 // Cracked Restricted ALU operations.
1070 // Here the two ALU ops can actually be done in parallel and therefore the
1073 // ALU ops are 3 cycles each.
1082 // Cracked instruction made of two ALU ops.
1084 // One of the ALU ops is restricted and takes 3 dispatches.
1097 // Cracked instruction made of two ALU ops.
1099 // Both of the ALU ops are restricted and take 3 dispatches.
1106 // Cracked ALU instruction composed of three consecutive 2 cycle loads for a
1107 // total of 6 cycles. All of the ALU operations are also restricted so each
1115 // Cracked instruction made of two ALU ops.
1133 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1167 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1186 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1205 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1236 // Instruction cracked into three pieces. One Load and two ALU operations.
1237 // The Load and one of the ALU ops cannot be run at the same time and so the
1238 // latencies are added together for 6 cycles. The remainaing ALU is 2 cycles.
1239 // Both the load and the ALU that depends on it are restricted and so they take
1240 // a total of 7 dispatches. The final 2 dispatches come from the second ALU op.
1249 // Cracked instruction made up of a Store and an ALU. The ALU does not depend on
1259 // Cracked instruction made up of a Load and an ALU. The ALU does not depend on
1268 // Cracked instruction made up of a Load and an ALU. The ALU does not depend on
1271 // are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline
1272 // is required for the ALU.
1326 // Five Cycle Branch with a 2 Cycle ALU Op