| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 24 ADDC = 0x01, enumerator
80 case ADDC: in lanaiAluCodeToString()
106 .Case("addc", ADDC) in stringToLanaiAluCode()
123 return AluCode::ADDC; in isdToLanaiAluCode()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb/ |
| H A D | long.ll | 100 define i64 @f9a(i64 %x, i64 %y) { ; ADDC with small negative imm => SUBS imm
112 define i64 @f9b(i64 %x, i64 %y) { ; ADDC with big negative imm => SUBS reg
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-cc-byval-split.ll | 48 ; CHECK32: renamable $r4 = ADDC killed renamable $r8, killed renamable $r[[REG1]], implicit-def…
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 269 ADDC, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelDAGToDAG.cpp | 731 case ISD::ADDC: in isAddressBase()
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| H A D | M68kISelLowering.cpp | 109 setOperationAction(ISD::ADDC, VT, Custom); in M68kTargetLowering()
1341 case ISD::ADDC: in LowerOperation()
2471 case ISD::ADDC: in LowerADDC_ADDE_SUBC_SUBE()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 39 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). enumerator
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| H A D | HexagonISelDAGToDAG.cpp | 762 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c in SelectAddSubCarry()
897 case HexagonISD::ADDC: in Select()
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| H A D | HexagonISelLowering.cpp | 1879 case HexagonISD::ADDC: return "HexagonISD::ADDC"; in getTargetNodeName()
3139 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(), in LowerAddSubCarry()
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| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | horizontal-list.ll | 942 ; CHECK-NEXT: [[ADDC:%.*]] = fadd fast float [[B:%.*]], 3.000000e+00
943 ; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[A:%.*]], [[ADDC]]
959 ; THRESHOLD-NEXT: [[ADDC:%.*]] = fadd fast float [[B:%.*]], 3.000000e+00
960 ; THRESHOLD-NEXT: [[ADD:%.*]] = fadd fast float [[A:%.*]], [[ADDC]]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 108 ADDC, // Add with carry enumerator
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| H A D | ARMISelLowering.cpp | 1705 MAKE_CASE(ARMISD::ADDC) in getTargetNodeName()
4895 Value = DAG.getNode(ARMISD::ADDC, dl, in getARMXALUOOp()
5003 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); in LowerUnsignedALUO()
12698 AddcSubcNode->getOpcode() != ARMISD::ADDC) || in AddCombineTo64bitMLAL()
12844 if (AddcNode->getOpcode() != ARMISD::ADDC) in AddCombineTo64bitUMAAL()
12894 if ((AddcNode->getOpcode() == ARMISD::ADDC) && in PerformUMLALCombine()
12930 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC in PerformAddcSubcCombine()
12931 : ARMISD::ADDC; in PerformAddcSubcCombine()
18600 case ARMISD::ADDC: in PerformDAGCombine()
19783 case ARMISD::ADDC: in computeKnownBitsForTargetNode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 303 case ISD::ADDC: return "addc"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 2497 case ISD::ADDC: in ExpandIntegerResult()
2935 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
2941 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3037 if (N->getOpcode() == ISD::ADDC) { in ExpandIntRes_ADDSUBC()
3038 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 533 case ISD::ADDC: in Select()
837 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
838 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 186 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 134 (instregex "ADDC(8)?(O)?$"),
1040 (instregex "ADDC(8)?(O)?_rec$"),
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| H A D | P10InstrResources.td | 1230 ADDC, ADDC8,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 124 setOperationAction(ISD::ADDC, MVT::i32, Legal); in ARCTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1655 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1661 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
3016 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3172 case ISD::ADDC: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 214 if (Opc == ISD::ADDC) { in selectAddE()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 824 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 543 defm ADDC : Arith<0b0110, "addc", adde, 1, [SR]>;
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 524 setOperationAction(ISD::ADDC, MVT::i32, Legal); in NVPTXTargetLowering()
529 setOperationAction(ISD::ADDC, MVT::i64, Legal); in NVPTXTargetLowering()
|