Searched refs:ABDS (Results 1 – 7 of 7) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 655 ABDS, enumerator
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 237 case ISD::ABDS: return "abds"; in getOperationName()
|
| H A D | DAGCombiner.cpp | 9866 unsigned ABDOpcode = (Opc0 == ISD::SIGN_EXTEND) ? ISD::ABDS : ISD::ABDU; in combineABSToABD()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 833 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1050 setOperationAction(ISD::ABDS, VT, Legal); in AArch64TargetLowering()
1178 setOperationAction(ISD::ABDS, VT, Custom); in AArch64TargetLowering()
4813 : ISD::ABDS; in LowerINTRINSIC_WO_CHAIN()
5599 case ISD::ABDS: in LowerOperation()
13844 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
13855 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
16633 return convertMergedOpToPredOp(N, ISD::ABDS, DAG, true); in performIntrinsicCombine()
16803 N->getOperand(0).getOpcode() == ISD::ABDS)) { in performExtendCombine()
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 382 def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 274 setOperationAction(ISD::ABDS, VT, Legal); in addMVEVectorTypes()
15409 case ISD::ABDS: in FlattenVectorShuffle()
|