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/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dframe-chain.ll21 ; LEAF-FP-AAPCS-LABEL: leaf:
78 ; FP-AAPCS-LABEL: non_leaf:
79 ; FP-AAPCS: @ %bb.0:
81 ; FP-AAPCS-NEXT: push {lr}
87 ; FP-AAPCS-NEXT: .pad #8
90 ; FP-AAPCS-NEXT: bl leaf
93 ; FP-AAPCS-NEXT: pop {r1}
95 ; FP-AAPCS-NEXT: pop {pc}
110 ; NOFP-AAPCS: @ %bb.0:
160 ; FP-AAPCS: @ %bb.0:
[all …]
H A Dframe-access.ll103 ; CHECK-AAPCS: mov r11, sp
111 ; CHECK-AAPCS: mov r0, r11
140 ; CHECK-AAPCS: mov r11, sp
150 ; CHECK-AAPCS: mov r0, r11
152 ; CHECK-AAPCS: mov r0, r11
154 ; CHECK-AAPCS: mov r0, r11
170 ; CHECK-AAPCS: mov r11, sp
175 ; CHECK-AAPCS: mov r5, r11
202 ; CHECK-AAPCS: mov r11, sp
407 ; CHECK-AAPCS: mov r11, sp
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dframe-chain.ll21 ; LEAF-FP-AAPCS-LABEL: leaf:
22 ; LEAF-FP-AAPCS: @ %bb.0:
42 ; LEAF-NOFP-AAPCS-LABEL: leaf:
73 ; FP-AAPCS-LABEL: non_leaf:
74 ; FP-AAPCS: @ %bb.0:
79 ; FP-AAPCS-NEXT: .pad #8
82 ; FP-AAPCS-NEXT: bl leaf
101 ; NOFP-AAPCS-LABEL: non_leaf:
102 ; NOFP-AAPCS: @ %bb.0:
105 ; NOFP-AAPCS-NEXT: .pad #8
[all …]
H A Darm-abi-attr.ll1 ; RUN: llc -mtriple=arm-linux-gnu < %s | FileCheck %s --check-prefix=AAPCS
7 ; RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s --check-prefix=AAPCS
9 ; RUN: FileCheck %s --check-prefix=AAPCS
11 ; RUN: FileCheck %s --check-prefix=AAPCS
13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
20 ; AAPCS: sub sp, sp, #8
21 ; AAPCS-NOT: bic
H A Dlarge-vector.ll2 …iple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS
13 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #8
14 ; CHECK-AAPCS: vld1.64 {d0, d1}, [r[[BASE]]]
15 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #24
16 ; CHECK-AAPCS: vld1.64 {d2, d3}, [r[[BASE]]]
33 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #8
34 ; CHECK-AAPCS: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]!
35 ; CHECK-AAPCS: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
H A Dtail-call.ll6 ; RUN: | FileCheck %s -check-prefix CHECK-TAIL-AAPCS -check-prefix CHECK
45 ; CHECK-TAIL-AAPCS: b variadic
56 ; CHECK-TAIL-AAPCS: b variadic
64 ; that %z is passed in r1-r2 if APCS is used, contrary to AAPCS where r2-r3
70 ; CHECK-TAIL-AAPCS: bl variadic
83 ; CHECK-TAIL-AAPCS: b variadic
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
H A Dv7k-abi-align.ll141 ; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give
H A Dinterrupt-attr.ll35 ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
H A Dfloat-helpers.s12 ; floating-point helper functions to always use the base AAPCS (soft-float)
20 ; * all functions use base AAPCS
24 ; * all non Runtime ABI helper functions use AAPCS VFP
34 ; In all cases we must use base AAPCS when calling a helper function from
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Di1-contents.ll7 ; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
18 ; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
31 ; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
H A Dargument-blocks.ll2 …c -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS
44 ; CHECK-AAPCS: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp, #8]
H A Darm64-aapcs.ll88 ; Under AAPCS variadic functions have the same calling convention as
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/Windows/
H A Daapcs.ll3 ; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned,
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dtail-call-r9.ll6 ; the destination address. It's callee-saved in AAPCS.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td126 // ARM AAPCS (EABI) Calling Convention, common parts
156 // ARM AAPCS (EABI) Calling Convention
203 // ARM AAPCS-VFP (EABI) Calling Convention
274 // AAPCS, and also preserves all floating point registers.
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
306 // This AAPCS alternative makes sure the frame index slots match the push
H A DARM.td551 "Create an AAPCS compliant frame chain">;
555 "Create an AAPCS compliant frame chain "
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/ARM/
H A Dattribute-0.s163 @CHECK-OBJ-NEXT: Description: AAPCS
170 @CHECK-OBJ-NEXT: Description: AAPCS
H A Dattribute-1.s149 @CHECK-OBJ-NEXT: Description: AAPCS VFP
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-eabi_attribute.s163 @ CHECK-OBJ-NEXT: Description: AAPCS VFP
169 @ CHECK-OBJ-NEXT: Description: AAPCS
/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst100 AAPCS section in Considerations
103 The ARM procedure call standard (AAPCS) defines the ABI for passing vectors between functions in re…
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td38 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
437 // Darwin variants of AAPCS.
457 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DCodeGenOptions.def455 /// Whether to follow the AAPCS enforcing at least one read before storing to a volatile bitfield
461 /// Whether to not follow the AAPCS that enforces volatile bit-field access width to be
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DTargetInfo.cpp5499 AAPCS = 0, enumerator
5803 if (Kind != AArch64ABIInfo::AAPCS) in classifyArgumentType()
5826 if (Kind == AArch64ABIInfo::AAPCS) { in classifyArgumentType()
6298 AAPCS = 1, enumerator
6555 case AAPCS: return llvm::CallingConv::ARM_AAPCS; in getABIDefaultCC()
6603 if (getABIKind() == ARMABIInfo::AAPCS || in classifyHomogeneousAggregate()
6692 getABIKind() == ARMABIInfo::AAPCS) { in classifyArgumentType()
7078 getABIKind() == ARMABIInfo::AAPCS) { in EmitVAArg()
11587 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS; in getTargetCodeGenInfo()
11614 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; in getTargetCodeGenInfo()

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