Home
last modified time | relevance | path

Searched refs:xcc_mask (Results 1 – 25 of 30) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c68 uint32_t xcc_mask; in gfxhub_v1_2_setup_vm_pt_regs() local
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
125 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_system_aperture_regs() argument
437 uint32_t xcc_mask; in gfxhub_v1_2_gart_enable() local
439 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_enable()
478 uint32_t xcc_mask; in gfxhub_v1_2_gart_disable() local
480 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_disable()
536 uint32_t xcc_mask; in gfxhub_v1_2_set_fault_enable_default() local
538 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_set_fault_enable_default()
585 uint32_t xcc_mask; in gfxhub_v1_2_init() local
[all …]
H A Daqua_vanjaram.c280 { GC_HWIP, adev->gfx.xcc_mask }, in aqua_vanjaram_ip_map_init()
318 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_calc_xcp_mode()
370 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()
490 num_xcp = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_get_xcp_res_info()
524 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()
548 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()
611 switch (NUM_XCC(adev->gfx.xcc_mask)) { in __aqua_vanjaram_update_supported_modes()
663 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_switch_partition_mode()
727 uint32_t xcc_mask; in aqua_vanjaram_get_xcp_mem_id() local
745 if (r || !xcc_mask) in aqua_vanjaram_get_xcp_mem_id()
[all …]
H A Dgfx_v9_4_3.c337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_mec_init()
800 NUM_XCC(adev->gfx.xcc_mask) / in gfx_v9_4_3_switch_compute_partition()
1009 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_alloc_ip_dump()
1061 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_init()
1176 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_fini()
1315 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_constants_init()
1392 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1485 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_rlc_stop()
[all …]
H A Dta_ras_if.h154 uint16_t xcc_mask; member
H A Damdgpu_gfx.c208 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
1041 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
1042 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); in amdgpu_gfx_ras_error_func() local
1050 for_each_inst(i, xcc_mask) in amdgpu_gfx_ras_error_func()
1369 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()
1493 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_run_cleaner_shader()
H A Dgmc_v9_0.c1944 uint32_t xcc_mask; in gmc_v9_0_init_acpi_mem_ranges() local
1946 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gmc_v9_0_init_acpi_mem_ranges()
1947 xcc_mask = (1U << num_xcc) - 1; in gmc_v9_0_init_acpi_mem_ranges()
1949 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
2178 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
H A Damdgpu_vm.h513 uint32_t xcc_mask);
H A Dnbio_v7_9.c436 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
H A Damdgpu_gfx.h456 uint16_t xcc_mask; member
H A Damdgpu_virt.c1067 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
H A Damdgpu_discovery.c748 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1038 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1337 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1434 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
H A Damdgpu_vm.c1661 uint32_t xcc_mask) in amdgpu_vm_flush_compute_tlb() argument
1681 for_each_inst(xcc, xcc_mask) { in amdgpu_vm_flush_compute_tlb()
H A Dsdma_v4_4_2.c144 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
149 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
H A Damdgpu_psp.c1861 ras_cmd->ras_in_message.init_flags.xcc_mask = in psp_ras_initialize()
1862 adev->gfx.xcc_mask; in psp_ras_initialize()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c141 NUM_XCC(node->xcc_mask), in allocate_mqd()
576 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
581 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
600 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
606 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
626 uint32_t xcc_mask = mm->dev->xcc_mask; in check_preemption_failed_v9_4_3() local
631 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
695 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v9_4_3()
776 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_mqd_v9_4_3() local
785 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
[all …]
H A Dkfd_mqd_manager.c80 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()
109 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
110 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask()
H A Dkfd_device_queue_manager.c148 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
151 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
520 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_trap_handler_settings() local
524 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
794 uint32_t xcc_mask = dev->xcc_mask; in dbgdev_wave_reset_wavefronts() local
841 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
1468 uint32_t xcc_mask = dqm->dev->xcc_mask; in set_pasid_vmid_mapping() local
1471 for_each_inst(xcc_id, xcc_mask) { in set_pasid_vmid_mapping()
1483 uint32_t xcc_mask = dqm->dev->xcc_mask; in init_interrupts() local
2885 NUM_XCC(dqm->dev->xcc_mask)); in allocate_hiq_sdma_mqd()
[all …]
H A Dkfd_queue.c309 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_acquire_buffers()
356 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_release_buffers()
441 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); in kfd_queue_ctx_save_restore_size()
H A Dkfd_device.c687 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
710 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
868 &node->xcc_mask); in kgd2kfd_device_init()
871 node->xcc_mask = in kgd2kfd_device_init()
872 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
H A Dkfd_debug.c467 uint32_t xcc_mask = pdd->dev->xcc_mask; in kfd_dbg_trap_set_dev_address_watch() local
481 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
1098 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
H A Dkfd_topology.c463 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
531 NUM_XCC(dev->gpu->xcc_mask)); in node_show()
1101 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()
1672 int num_xcc = NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()
1678 start = ffs(knode->xcc_mask) - 1; in fill_in_l2_l3_pcache()
1803 start = ffs(kdev->xcc_mask) - 1; in kfd_fill_cache_non_crat_info()
1804 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
H A Dkfd_device_queue_manager.h368 ffs(dqm->dev->xcc_mask) - 1); in update_dqm_wait_times()
H A Dkfd_priv.h272 uint32_t xcc_mask; /* Instance mask of XCCs present */ member
1524 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); in kfd_flush_tlb()
H A Dkfd_process.c307 &max_waves_per_cu, ffs(dev->xcc_mask) - 1); in kfd_get_cu_occupancy()
317 wave_cnt += (NUM_XCC(dev->xcc_mask) * in kfd_get_cu_occupancy()
H A Dkfd_process_queue_manager.c1116 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()

12