| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
|
| H A D | dce_hwseq.h | 1300 unsigned int tg_inst);
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.h | 86 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtot…
88 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
200 uint32_t tg_inst,
|
| H A D | dc_dmub_srv.c | 362 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtot… in dc_dmub_srv_drr_update_cmd() argument
370 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; in dc_dmub_srv_drr_update_cmd()
378 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) in dc_dmub_srv_set_drr_manual_trigger_cmd() argument
384 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; in dc_dmub_srv_set_drr_manual_trigger_cmd()
1708 uint32_t tg_inst, in dc_dmub_srv_fams2_drr_update() argument
1719 cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst; in dc_dmub_srv_fams2_drr_update()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/virtual/ |
| H A D | virtual_stream_encoder.c | 93 int tg_inst) in virtual_dig_connect_to_otg() argument
98 int tg_inst, in virtual_setup_stereo_sync() argument
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_stream_encoder.c | 1482 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1485 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1491 int tg_inst) in enc1_dig_connect_to_otg() argument
1495 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1501 uint32_t tg_inst = 0; in enc1_dig_source_otg() local
1504 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
1506 return tg_inst; in enc1_dig_source_otg()
|
| H A D | dcn10_stream_encoder.h | 687 int tg_inst, bool enable);
719 int tg_inst);
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.c | 1488 int tg_inst, bool enable) in setup_stereo_sync() argument
1491 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1497 int tg_inst) in dig_connect_to_otg() argument
1501 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1507 uint32_t tg_inst = 0; in dig_source_otg() local
1510 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1512 return tg_inst; in dig_source_otg()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | stream_encoder.h | 216 int tg_inst,
224 int tg_inst);
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 3661 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
3676 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state()
3686 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
3689 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
3690 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
3692 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
3693 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
3700 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
3711 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
3867 int tg_inst = pool->timing_generator_count - 1; in acquire_otg_master_pipe_for_stream() local
[all …]
|
| H A D | dc.c | 1369 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local
1376 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required()
1384 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required()
1697 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_boot_timing() local
1727 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_boot_timing()
1739 if (tg_inst >= dc->res_pool->timing_generator_count) { in dc_validate_boot_timing()
1744 if (tg_inst != link->link_enc->preferred_engine) { in dc_validate_boot_timing()
1749 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_boot_timing()
1834 tg_inst, &pix_clk_100hz); in dc_validate_boot_timing()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 1901 uint8_t tg_inst; member
5161 uint32_t tg_inst; member
|