drm/amd/display: Fix BT2020 YCbCr limited/full range input

[Why]
BT2020 YCbCr input is not handled properly when full range
quantization is used and limited range is not supported at all.

[How]
- A

drm/amd/display: Fix BT2020 YCbCr limited/full range input

[Why]
BT2020 YCbCr input is not handled properly when full range
quantization is used and limited range is not supported at all.

[How]
- Add enums for BT2020 YCbCr limited/full range
- Add limited range CSC matrix

Reviewed-by: Krunoslav Kovac <[email protected]>
Signed-off-by: Ilya Bakoulin <[email protected]>
Signed-off-by: Roman Li <[email protected]>
Tested-by: Robert Mader <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Remove useless assignments and variables

[WHAT & HOW]
misc0, temp and split_pipe are assigned but immediately re-assigned
to other values. The early assignments are useless and are

drm/amd/display: Remove useless assignments and variables

[WHAT & HOW]
misc0, temp and split_pipe are assigned but immediately re-assigned
to other values. The early assignments are useless and are removed.
Unused variables are removed as well.

This fixes 5 UNUSED_VALUE issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
Signed-off-by: Tom Chung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Adjust incorrect indentations and spaces

This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <[email protected]>

drm/amd/display: Adjust incorrect indentations and spaces

This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Move all linux includes into OS types

Move all linux includes into OS types.

Acked-by: Alan Liu <[email protected]>
Signed-off-by: Harry Wentland <[email protected]>
Tested-

drm/amd/display: Move all linux includes into OS types

Move all linux includes into OS types.

Acked-by: Alan Liu <[email protected]>
Signed-off-by: Harry Wentland <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Program ACP related register

- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration

R

drm/amd/display: Program ACP related register

- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration

Reviewed-by: Harry Wentland <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alan Liu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce

[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.

This patch fixes it by

drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce

[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.

This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dce directory.

Reviewed-by: Rodrigo Siqueira <[email protected]>
Acked-by: Stylon Wang <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Add DPCD writes at key points

This reverts commit "Revert "Add DPCD writes at key points" ".
The following patch will fix the system hang issue.

v2: squash in indentation warning f

drm/amd/display: Add DPCD writes at key points

This reverts commit "Revert "Add DPCD writes at key points" ".
The following patch will fix the system hang issue.

v2: squash in indentation warning fix

Signed-off-by: Leo (Hanghong) Ma <[email protected]>
Acked-by: Mikita Lipski <[email protected]>
Reviewed-by: Aric Cyr <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Fix HDMI deep color output for DCE 6-11.

This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.

It will hopefully also

drm/amd/display: Fix HDMI deep color output for DCE 6-11.

This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.

It will hopefully also provide fixes for other DCE's up to
DCE-11, assuming those will need similar fixes, but i could
not test that for HDMI due to lack of suitable hw, so viewer
discretion is advised.

dce110_stream_encoder_hdmi_set_stream_attribute() is used for
HDMI setup on all DCE's and is missing color_depth assignment.

dce110_program_pix_clk() is used for pixel clock setup on HDMI
for DCE 6-11, and is missing color_depth assignment.

Additionally some of the underlying Atombios specific encoder
and pixelclock setup functions are missing code which is in
the classic amdgpu kms modesetting path and the in the radeon
kms driver for DCE6/DCE8.

encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
and radeon kms classic drivers. Added here, but untested due to
lack of suitable test hw.

encoder_control_digx_v4() - Added missing setup code.
Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
output at 10 bpc and 12 bpc.

Note that encoder_control_digx_v5() has proper setup code in place
and is used, e.g., by DCE-11.2, but this code wasn't used for deep
color setup due to the missing cntl.color_depth setup in the calling
function for HDMI.

set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
kms. Added here, but untested due to lack of hw.

set_pixel_clock_v6() - Missing setup code added. Successfully tested
on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
deep color output with 10 bpc or 12 bpc.

Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")

Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Mario Kleiner <[email protected]>
Cc: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display/dc/dce/dce_stream_encoder: Remove unused variable 'regval'

Fixes the following W=1 kernel build warning(s):

drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c: In fu

drm/amd/display/dc/dce/dce_stream_encoder: Remove unused variable 'regval'

Fixes the following W=1 kernel build warning(s):

drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c: In function ‘dce110_update_generic_info_packet’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:70:11: warning: variable ‘regval’ set but not used [-Wunused-but-set-variable]

Cc: Harry Wentland <[email protected]>
Cc: Leo Li <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Christian König" <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: George Shen <[email protected]>
Cc: Eric Bernstein <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Move common speakersToChannels definition to hw_shared.h

Signed-off-by: Eric Bernstein <[email protected]>
Acked-by: Bindu Ramamurthy <[email protected]>
Signed-off-by: Alex Deuc

drm/amd/display: Move common speakersToChannels definition to hw_shared.h

Signed-off-by: Eric Bernstein <[email protected]>
Acked-by: Bindu Ramamurthy <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Rename set_mst_bandwidth to align with DP spec

[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the al

drm/amd/display: Rename set_mst_bandwidth to align with DP spec

[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the allocation sequence
described in the DP spec.

[How]
Rename the function set_mst_bandwidth to set_throttled_vcp_size.

Signed-off-by: George Shen <[email protected]>
Acked-by: Aurabindo Pillai <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: remove set but not used variable 'speakers' in dce_stream_encoder.c

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:1339:11:

drm/amd/display: remove set but not used variable 'speakers' in dce_stream_encoder.c

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:1339:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable]

It is introduced by commit 4562236b3bc0 ("drm/amd/dc:
Add dc display driver (v2)"), but never used, so remove it.

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Zheng Bin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: rename DCN1_0 kconfig to DCN

Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.

Change it to "dcn" to make it generic

Signed-off-by: Bhawanpreet Lakh

drm/amd/display: rename DCN1_0 kconfig to DCN

Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.

Change it to "dcn" to make it generic

Signed-off-by: Bhawanpreet Lakha <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP

[Why]
It is confusing to sinks if we send VSC SDP only on some format. Today we
signal colorimetry format using MSA while in

drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP

[Why]
It is confusing to sinks if we send VSC SDP only on some format. Today we
signal colorimetry format using MSA while in formats like sRGB.
But when we switch to BT2020 we set the bit to ignore MSA colorimetry and
instead use the colorimetry information in the VSC SDP.

But if sink supports signaling of colorimetry via VSC SDP we should always
set the MSA MISC1 bit 6, instead of doing so selectively.

[How]
If sink supports signaling of colorimetry via VSC SDP, and we are sending
the colorimetry info via VSC SDP with packet revision 05h, then always
set MSA MISC1 bit 6.

Signed-off-by: Anthony Koo <[email protected]>
Reviewed-by: Aric Cyr <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: enabling seamless boot sequence for dcn2

[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MP

drm/amd/display: enabling seamless boot sequence for dcn2

[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.

This is part 2 of 2 for seamless boot NV10

Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset

[why]
hdmi data scramble and tmds rate is not reset during pipe reset.

[how]
reset hdmi tmds rate and data scramble on pipe res

drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset

[why]
hdmi data scramble and tmds rate is not reset during pipe reset.

[how]
reset hdmi tmds rate and data scramble on pipe reset

Signed-off-by: Wenjing Liu <[email protected]>
Reviewed-by: Chris Park <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTO

[Why]
-Pass and use pixel clock in 100 Hz to Audio for HDMI
audio DTO for Audio wall clock programming so audio DTO gets

drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTO

[Why]
-Pass and use pixel clock in 100 Hz to Audio for HDMI
audio DTO for Audio wall clock programming so audio DTO gets
increased precision for timings with /1001 factor.
-For HDMI TMDS for N and CTS ACR tables are based on 10 KHz
units, these does not need to be modified as N and CTS values
are still valid using current tables.

Signed-off-by: Nevenko Stupar <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd: drop dependencies on drm_os_linux.h

Fix so no files in drm/amd/ depends on the
deprecated drm_os_linux.h header file.

It was done manually:
- remove drm_os_linux.h from drmP.h
- fix all bu

drm/amd: drop dependencies on drm_os_linux.h

Fix so no files in drm/amd/ depends on the
deprecated drm_os_linux.h header file.

It was done manually:
- remove drm_os_linux.h from drmP.h
- fix all build errros

Signed-off-by: Sam Ravnborg <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Cc: "Christian König" <[email protected]>
Cc: "David (ChunMing) Zhou" <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

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drm/amd/display: Refactor DIO stream encoder

* Pull duplicate audio_clock_info struct to stream_encoder.h
* Generalize sec_gsp7* to sec_gsp_pps*
* Expose enc1 and enc2 stream encoder audio funcs

Si

drm/amd/display: Refactor DIO stream encoder

* Pull duplicate audio_clock_info struct to stream_encoder.h
* Generalize sec_gsp7* to sec_gsp_pps*
* Expose enc1 and enc2 stream encoder audio funcs

Signed-off-by: Eric Bernstein <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: color space ycbcr709 support

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Duke Du <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed

drm/amd/display: color space ycbcr709 support

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Duke Du <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Pass SDP spliting in parameters

pass SDP splitting when setting stream attributes for future use

Signed-off-by: Nikola Cornij <[email protected]>
Reviewed-by: Tony Cheng <Tony.

drm/amd/display: Pass SDP spliting in parameters

pass SDP splitting when setting stream attributes for future use

Signed-off-by: Nikola Cornij <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: fix DP 422 VID_M half the rate issue.

[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using hal

drm/amd/display: fix DP 422 VID_M half the rate issue.

[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444.

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Nikola Cornij <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Connect dig_fe to otg directly instead of calling bios

[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other

drm/amd/display: Connect dig_fe to otg directly instead of calling bios

[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.

[How] Program dig_soruce_select register directly

Signed-off-by: hersen wu <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: dp interlace MSA timing programming for Interlace mode.

[Why]
DP compliance box shows wrong MSA data.

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Jun Lei <Jun.L

drm/amd/display: dp interlace MSA timing programming for Interlace mode.

[Why]
DP compliance box shows wrong MSA data.

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/display: Use 100 Hz precision for pipe pixel clocks

[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.

[How]
Store and communicate

drm/amd/display: Use 100 Hz precision for pipe pixel clocks

[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.

[How]
Store and communicate pixel clocks with 100 Hz accuracy from
dc_crtc_timing through to BIOS command table setpixelclock call.

Signed-off-by: Ken Chalmers <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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